================
@@ -1516,48 +1536,206 @@ let Predicates = [FeatureVector] in {
}
}
+//===----------------------------------------------------------------------===//
+// Support for 128-bit integer values in vector registers
+//===----------------------------------------------------------------------===//
+
+// Loads and stores.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (load bdxaddr12only:$addr)),
+ (VL bdxaddr12only:$addr)>;
+ def : Pat<(store (i128 VR128:$src), bdxaddr12only:$addr),
+ (VST VR128:$src, bdxaddr12only:$addr)>;
+}
+
+// Full i128 move from GPR pair.
+let Predicates = [FeatureVector] in
+ def : Pat<(i128 (or (zext GR64:$x), (shl (anyext GR64:$y), (i32 64)))),
+ (VLVGP GR64:$y, GR64:$x)>;
+
+// Any-extensions from GPR to i128.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (anyext GR32:$x)), (VLVGP32 GR32:$x, GR32:$x)>;
+ def : Pat<(i128 (anyext GR64:$x)), (VLVGP GR64:$x, GR64:$x)>;
+}
+
+// Any-extending loads into i128.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (extloadi8 bdxaddr12only:$addr)),
+ (VLREPB bdxaddr12only:$addr)>;
+ def : Pat<(i128 (extloadi16 bdxaddr12only:$addr)),
+ (VLREPH bdxaddr12only:$addr)>;
+ def : Pat<(i128 (extloadi32 bdxaddr12only:$addr)),
+ (VLREPF bdxaddr12only:$addr)>;
+ def : Pat<(i128 (extloadi64 bdxaddr12only:$addr)),
+ (VLREPG bdxaddr12only:$addr)>;
+}
+
+// Truncations from i128 to GPR.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i32 (trunc (i128 VR128:$vec))),
+ (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 3), subreg_l32)>;
+ def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 32)))),
+ (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 2), subreg_l32)>;
+ def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 64)))),
+ (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 1), subreg_l32)>;
+ def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 96)))),
+ (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 0), subreg_l32)>;
+ def : Pat<(i64 (trunc (i128 VR128:$vec))),
+ (VLGVG VR128:$vec, zero_reg, 1)>;
+ def : Pat<(i64 (trunc (srl (i128 VR128:$vec), (i32 64)))),
+ (VLGVG VR128:$vec, zero_reg, 0)>;
+}
+
+// Truncating stores from i128.
+let Predicates = [FeatureVector] in {
+ def : Pat<(truncstorei8 (i128 VR128:$x), bdxaddr12only:$addr),
+ (VSTEB VR128:$x, bdxaddr12only:$addr, 15)>;
+ def : Pat<(truncstorei16 (i128 VR128:$x), bdxaddr12only:$addr),
+ (VSTEH VR128:$x, bdxaddr12only:$addr, 7)>;
+ def : Pat<(truncstorei32 (i128 VR128:$x), bdxaddr12only:$addr),
+ (VSTEF VR128:$x, bdxaddr12only:$addr, 3)>;
+ def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 32)),
bdxaddr12only:$addr),
+ (VSTEF VR128:$x, bdxaddr12only:$addr, 2)>;
+ def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 64)),
bdxaddr12only:$addr),
+ (VSTEF VR128:$x, bdxaddr12only:$addr, 1)>;
+ def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 96)),
bdxaddr12only:$addr),
+ (VSTEF VR128:$x, bdxaddr12only:$addr, 0)>;
+ def : Pat<(truncstorei64 (i128 VR128:$x), bdxaddr12only:$addr),
+ (VSTEG VR128:$x, bdxaddr12only:$addr, 1)>;
+ def : Pat<(truncstorei64 (srl (i128 VR128:$x), (i32 64)),
bdxaddr12only:$addr),
+ (VSTEG VR128:$x, bdxaddr12only:$addr, 0)>;
+}
+
+// Zero-extensions from GPR to i128.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (zext8 (anyext GR32:$x))),
+ (VLVGB (VGBM 0), GR32:$x, zero_reg, 15)>;
+ def : Pat<(i128 (zext16 (anyext GR32:$x))),
+ (VLVGH (VGBM 0), GR32:$x, zero_reg, 7)>;
+ def : Pat<(i128 (zext GR32:$x)),
+ (VLVGF (VGBM 0), GR32:$x, zero_reg, 3)>;
+ def : Pat<(i128 (zext GR64:$x)),
+ (VLVGG (VGBM 0), GR64:$x, zero_reg, 1)>;
+}
+
+// Zero-extending loads into i128.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (zextloadi8 bdxaddr12only:$addr)),
+ (VLEB (VGBM 0), bdxaddr12only:$addr, 15)>;
+ def : Pat<(i128 (zextloadi16 bdxaddr12only:$addr)),
+ (VLEH (VGBM 0), bdxaddr12only:$addr, 7)>;
+ def : Pat<(i128 (zextloadi32 bdxaddr12only:$addr)),
+ (VLEF (VGBM 0), bdxaddr12only:$addr, 3)>;
+ def : Pat<(i128 (zextloadi64 bdxaddr12only:$addr)),
+ (VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;
+}
+
+// In-register i128 sign-extensions.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (sext_inreg VR128:$x, i8)),
+ (VSRAB (VREPB VR128:$x, 15), (VREPIB 120))>;
+ def : Pat<(i128 (sext_inreg VR128:$x, i16)),
+ (VSRAB (VREPH VR128:$x, 7), (VREPIB 112))>;
+ def : Pat<(i128 (sext_inreg VR128:$x, i32)),
+ (VSRAB (VREPF VR128:$x, 3), (VREPIB 96))>;
+ def : Pat<(i128 (sext_inreg VR128:$x, i64)),
+ (VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>;
+}
+
+// Sign-extensions from GPR to i128.
+let Predicates = [FeatureVector] in {
+ def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),
+ (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GR32:$x, subreg_l32)),
+ (SRAG (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GR32:$x, subreg_l32)), zero_reg, 63))>;
+ def : Pat<(i128 (sext_inreg (anyext GR32:$x), i16)),
+ (VLVGP (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GR32:$x, subreg_l32)),
+ (SRAG (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GR32:$x, subreg_l32)), zero_reg, 63))>;
+ def : Pat<(i128 (sext GR32:$x)),
+ (VLVGP (LGFR GR32:$x), (SRAG (LGFR GR32:$x), zero_reg, 63))>;
+ def : Pat<(i128 (sext GR64:$x)),
+ (VLVGP GR64:$x, (SRAG GR64:$x, zero_reg, 63))>;
+}
----------------
JonPsson1 wrote:
Confused about the order of GPR operands here: I thought the Most Significant
part was the first GPR operand to VLVGP, and would expect the sign bit vector
go there..?
https://github.com/llvm/llvm-project/pull/74625
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