================
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;
def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [IsStreamingCompatible], [ImmCheck<1,
ImmCheck0_1>]>;
-}
-let TargetGuard = "sve2p1" in {
def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone,
"aarch64_sve_fclamp", [], []>;
-def SVWHILEGE_COUNT : SInst<"svwhilege_{d}", "}lli", "QcQsQiQl", MergeNone,
"aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}", "}lli", "QcQsQiQl", MergeNone,
"aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILELE_COUNT : SInst<"svwhilele_{d}", "}lli", "QcQsQiQl", MergeNone,
"aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILELT_COUNT : SInst<"svwhilelt_{d}", "}lli", "QcQsQiQl", MergeNone,
"aarch64_sve_whilelt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILELO_COUNT : SInst<"svwhilelo_{d}", "}nni", "QcQsQiQl", MergeNone,
"aarch64_sve_whilelo_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILELS_COUNT : SInst<"svwhilels_{d}", "}nni", "QcQsQiQl", MergeNone,
"aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILEHI_COUNT : SInst<"svwhilehi_{d}", "}nni", "QcQsQiQl", MergeNone,
"aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
-def SVWHILEHS_COUNT : SInst<"svwhilehs_{d}", "}nni", "QcQsQiQl", MergeNone,
"aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEGE_COUNT : SInst<"svwhilege_{d}[_{1}]", "}lli", "QcQsQiQl",
MergeNone, "aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}[_{1}]", "}lli", "QcQsQiQl",
MergeNone, "aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILELE_COUNT : SInst<"svwhilele_{d}[_{1}]", "}lli", "QcQsQiQl",
MergeNone, "aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILELT_COUNT : SInst<"svwhilelt_{d}[_{1}]", "}lli", "QcQsQiQl",
MergeNone, "aarch64_sve_whilelt_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILELO_COUNT : SInst<"svwhilelo_{d}[_{1}]", "}nni", "QcQsQiQl",
MergeNone, "aarch64_sve_whilelo_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILELS_COUNT : SInst<"svwhilels_{d}[_{1}]", "}nni", "QcQsQiQl",
MergeNone, "aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILEHI_COUNT : SInst<"svwhilehi_{d}[_{1}]", "}nni", "QcQsQiQl",
MergeNone, "aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
+def SVWHILEHS_COUNT : SInst<"svwhilehs_{d}[_{1}]", "}nni", "QcQsQiQl",
MergeNone, "aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2,
ImmCheck2_4_Mul2>]>;
----------------
CarolineConcatto wrote:
The latest change in the ACLE now the signed and unsigned are represented in
only one intrinsic.
Now we only have 4 intrinsics instead of 8, and they are:
// All the intrinsics below are [SVE2.1 or SME2]
// Variants are also available for:
// _b16[_s64]_x2, _b32[_s64]_x2 and _b64[_s64]_x2$
// _b8[_u64]_x2, _b16[_u64]_x2, _b32[_u64]_x2 and _b64[_u64]_x2$
svboolx2_t svwhilege_b8[_s64]_x2(int64_t rn, int64_t rm);
svboolx2_t svwhilegt_b8[_s64]_x2(int64_t rn, int64_t rm);
svboolx2_t svwhilele_b8[_s64]_x2(int64_t rn, int64_t rm);
svboolx2_t svwhilelt_b8[_s64]_x2(int64_t rn, int64_t rm);
https://github.com/llvm/llvm-project/pull/75200
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