[clang-tools-extra] [flang] [clang] [compiler-rt] [llvm] [RISCV] Add bset optimization for left shift code (PR #71420)

[Ryan Taylor via cfe-commits]

https://github.com/rtayl updated https://github.com/llvm/llvm-project/pull/71420
>From 284c04113dcb3d683e8eaad3242d5bc5d0b4987d Mon Sep 17 00:00:00 2001
From: Ryan Taylor <rtay...@ventanamicro.com>
Date: Mon, 6 Nov 2023 10:54:17 -0500
Subject: [PATCH] [RISCV] Add bset optimization for left shift code

Changes:
  li a1, -1
  sll a0, a1, a0
  not a0, a0
  sext.w a0, a0
To:
  bset a0, x0, a0
  addiw a0, a0, -1w
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZb.td |  2 ++
 llvm/test/CodeGen/RISCV/rv64zbs.ll        | 26 +++++++++++++++++++----
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 0a19d3542d7b130..2bc927e214c952f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -554,6 +554,8 @@ def : Pat<(XLenVT (and (shiftop<srl> GPR:$rs1, (XLenVT 
GPR:$rs2)), 1)),
 
 def : Pat<(XLenVT (shiftop<shl> 1, (XLenVT GPR:$rs2))),
           (BSET (XLenVT X0), GPR:$rs2)>;
+def : Pat<(XLenVT (xor (shiftopw<riscv_sllw> -1, (XLenVT GPR:$rs2)), -1)),
+         (ADDIW (BSET (XLenVT X0), GPR:$rs2), -1)>;
 
 def : Pat<(XLenVT (and GPR:$rs1, BCLRMask:$mask)),
           (BCLRI GPR:$rs1, BCLRMask:$mask)>;
diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll 
b/llvm/test/CodeGen/RISCV/rv64zbs.ll
index ba43a304e6a39b9..3bbc5b22b69c23f 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -146,6 +146,24 @@ define signext i32 @bset_i32_no_mask(i32 signext %a, i32 
signext %b) nounwind {
   ret i32 %or
 }
 
+define signext i32 @bset_i32_not_mask(i32 signext %a) nounwind {
+; RV64I-LABEL: bset_i32_not_mask:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, -1
+; RV64I-NEXT:    sllw a0, a1, a0
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bset_i32_not_mask
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bset a0, zero, a0
+; RV64ZBS-NEXT:    addiw a0, a0, -1
+; RV64ZBS-NEXT:    ret
+  %notmask = shl nsw i32 -1, %a
+  %sub = xor i32 %notmask, -1
+  ret i32 %sub
+}
+
 define signext i32 @bset_i32_load(ptr %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: bset_i32_load:
 ; RV64I:       # %bb.0:
@@ -370,19 +388,19 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext 
%1) {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    beqz a0, .LBB19_2
+; RV64I-NEXT:    beqz a0, .LBB20_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB19_2:
+; RV64I-NEXT:  .LBB20_2:
 ; RV64I-NEXT:    tail bar@plt
 ;
 ; RV64ZBS-LABEL: bext_i32_trunc:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bext a0, a0, a1
-; RV64ZBS-NEXT:    beqz a0, .LBB19_2
+; RV64ZBS-NEXT:    beqz a0, .LBB20_2
 ; RV64ZBS-NEXT:  # %bb.1:
 ; RV64ZBS-NEXT:    ret
-; RV64ZBS-NEXT:  .LBB19_2:
+; RV64ZBS-NEXT:  .LBB20_2:
 ; RV64ZBS-NEXT:    tail bar@plt
   %3 = shl i32 1, %1
   %4 = and i32 %3, %0

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