https://github.com/sstwcw created
https://github.com/llvm/llvm-project/pull/71354
In a tagged union expression, there should be a space between the field name
and the data. Previously, the tag could be recognized as part of a dotted
identifier or a struct literal, and the space would be omitted.
>From 758fc8c9240452b90c3df2781429ae07699ef577 Mon Sep 17 00:00:00 2001
From: sstwcw <su3e8a96kzl...@posteo.net>
Date: Mon, 6 Nov 2023 03:26:02 +0000
Subject: [PATCH] [clang-format] Add space in Verilog tagged unions
In a tagged union expression, there should be a space between the field
name and the data. Previously, the tag could be recognized as part of a
dotted identifier or a struct literal, and the space would be omitted.
---
clang/lib/Format/TokenAnnotator.cpp | 9 ++++++++-
clang/unittests/Format/FormatTestVerilog.cpp | 14 ++++++++++++--
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Format/TokenAnnotator.cpp
b/clang/lib/Format/TokenAnnotator.cpp
index 729e7e370bf62ea..263125d5711a95b 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -4694,8 +4694,15 @@ bool TokenAnnotator::spaceRequiredBefore(const
AnnotatedLine &Line,
Left.isOneOf(TT_VerilogDimensionedTypeName, Keywords.kw_function)) {
return true;
}
+ // In a tagged union expression, there should be a space after the tag.
+ if (Right.isOneOf(tok::period, Keywords.kw_apostrophe) &&
+ Keywords.isVerilogIdentifier(Left) && Left.getPreviousNonComment() &&
+ Left.getPreviousNonComment()->is(Keywords.kw_tagged)) {
+ return true;
+ }
// Don't add spaces between a casting type and the quote or repetition
count
- // and the brace.
+ // and the brace. The case of tagged union expressions is handled by the
+ // previous rule.
if ((Right.is(Keywords.kw_apostrophe) ||
(Right.is(BK_BracedInit) && Right.is(tok::l_brace))) &&
!(Left.isOneOf(Keywords.kw_assign, Keywords.kw_unique) ||
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp
b/clang/unittests/Format/FormatTestVerilog.cpp
index 1c2692467987d9b..99d0fcca38c3993 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -359,6 +359,11 @@ TEST_F(FormatTestVerilog, Case) {
" arg);\n"
"endcase",
Style);
+
+ verifyFormat("case (v) matches\n"
+ " tagged Valid .n:\n"
+ " ;\n"
+ "endcase");
}
TEST_F(FormatTestVerilog, Coverage) {
@@ -1278,12 +1283,17 @@ TEST_F(FormatTestVerilog, StructLiteral) {
verifyFormat("c = '{'{1, 1.0}, '{2, 2.0}};");
verifyFormat("c = '{a: 0, b: 0.0};");
verifyFormat("c = '{a: 0, b: 0.0, default: 0};");
+ verifyFormat("d = {int: 1, shortreal: 1.0};");
+ verifyFormat("c = '{default: 0};");
+
+ // The identifier before the quote can be either a tag or a type case. There
+ // should be a space between the tag and the quote.
verifyFormat("c = ab'{a: 0, b: 0.0};");
verifyFormat("c = ab'{cd: cd'{1, 1.0}, ef: ef'{2, 2.0}};");
verifyFormat("c = ab'{cd'{1, 1.0}, ef'{2, 2.0}};");
- verifyFormat("d = {int: 1, shortreal: 1.0};");
verifyFormat("d = ab'{int: 1, shortreal: 1.0};");
- verifyFormat("c = '{default: 0};");
+ verifyFormat("x = tagged Add '{e1, 4, ed};");
+
auto Style = getDefaultStyle();
Style.SpacesInContainerLiterals = true;
verifyFormat("c = '{a : 0, b : 0.0};", Style);
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