llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-driver Author: Yingwei Zheng (dtcxzyw) <details> <summary>Changes</summary> [XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source high-performance RISC-V processor. This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the XiangShan processor series. Overview: https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/ It is based on the patch [D122556](https://reviews.llvm.org/D122556) by @<!-- -->SForeKeeper. The original patch hasn't been updated for a long time and it is out of sync with the current RTL design. Now ICT-CAS is about to complete the tape-out of NanHu core according to @<!-- -->poemonsense. So I posted this PR to add support for it. [Move elimination](https://github.com/dtcxzyw/llvm-project/commit/59f6e22bf12f67d799a7777f641853fec76c0aa8#diff-32270ea35a510b9a116a50cf5b922c46c194da7b0e0afe76576b8b2bef06556d) and macro fusions will be supported in subsequent PRs. --- Patch is 70.52 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/70232.diff 14 Files Affected: - (modified) clang/test/Driver/riscv-cpus.c (+14) - (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2) - (modified) llvm/lib/Target/RISCV/RISCV.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoD.td (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoF.td (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+21) - (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+2) - (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+2) - (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td (+2) - (added) llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td (+307) - (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+2) - (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s (+53) - (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s (+527) - (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s (+73) ``````````diff diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 3eaceedce685fc6..70f0a63336bd478 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -20,6 +20,17 @@ // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s +// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval" +// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d" + // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s @@ -62,6 +73,9 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s +// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" + // Check mtune alias CPU has resolved to the right CPU according XLEN. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s // MTUNE-GENERIC-32: "-tune-cpu" "generic" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index b2a04ebdbce628f..8e91eb4c62dd259 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index be93d5933d3329e..cb48ac4eeadd251 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -37,6 +37,7 @@ include "GISel/RISCVRegisterBanks.td" include "RISCVSchedRocket.td" include "RISCVSchedSiFive7.td" include "RISCVSchedSyntacoreSCR1.td" +include "RISCVSchedXiangShanNanHu.td" //===----------------------------------------------------------------------===// // RISC-V processors supported. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index 59312f02aeceb77..34becfafe77473d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -78,7 +78,7 @@ def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; } // Predicates = [HasStdExtD] foreach Ext = DExts in { - let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in { + let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in { defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", Ext>; defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", Ext>; defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", Ext>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index 8726245f1602ebf..3a5794bb2d19474 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>; } // Predicates = [HasStdExtF] foreach Ext = FExts in { - let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in { + let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in { defm FMADD_S : FPFMA_rrr_frm_m<OPC_MADD, 0b00, "fmadd.s", Ext>; defm FMSUB_S : FPFMA_rrr_frm_m<OPC_MSUB, 0b00, "fmsub.s", Ext>; defm FNMSUB_S : FPFMA_rrr_frm_m<OPC_NMSUB, 0b00, "fnmsub.s", Ext>; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index e4008d145ffa572..334e1f3f1d4521a 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -243,3 +243,24 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", FeatureStdExtZicbop, FeatureStdExtZicboz, FeatureVendorXVentanaCondOps]>; + +def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", + XiangShanNanHuModel, + [Feature64Bit, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs, + FeatureStdExtZkn, + FeatureStdExtZksed, + FeatureStdExtZksh, + FeatureStdExtSvinval, + FeatureStdExtZicbom, + FeatureStdExtZicboz]>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index 8fbc9afe267c562..bb9dfe5d0124098 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -206,7 +206,9 @@ def : ReadAdvance<ReadFAdd64, 0>; def : ReadAdvance<ReadFMul32, 0>; def : ReadAdvance<ReadFMul64, 0>; def : ReadAdvance<ReadFMA32, 0>; +def : ReadAdvance<ReadFMA32Addend, 0>; def : ReadAdvance<ReadFMA64, 0>; +def : ReadAdvance<ReadFMA64Addend, 0>; def : ReadAdvance<ReadFDiv32, 0>; def : ReadAdvance<ReadFDiv64, 0>; def : ReadAdvance<ReadFSqrt32, 0>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 96ebe8e3e67686a..822dc43d21f8392 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -936,7 +936,9 @@ def : ReadAdvance<ReadFMA16, 0>; def : ReadAdvance<ReadFMul32, 0>; def : ReadAdvance<ReadFMul64, 0>; def : ReadAdvance<ReadFMA32, 0>; +def : ReadAdvance<ReadFMA32Addend, 0>; def : ReadAdvance<ReadFMA64, 0>; +def : ReadAdvance<ReadFMA64Addend, 0>; def : ReadAdvance<ReadFDiv16, 0>; def : ReadAdvance<ReadFDiv32, 0>; def : ReadAdvance<ReadFDiv64, 0>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td index 960258c8bc7dfe8..06ad2075b073614 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td @@ -164,7 +164,9 @@ def : ReadAdvance<ReadFAdd64, 0>; def : ReadAdvance<ReadFMul32, 0>; def : ReadAdvance<ReadFMul64, 0>; def : ReadAdvance<ReadFMA32, 0>; +def : ReadAdvance<ReadFMA32Addend, 0>; def : ReadAdvance<ReadFMA64, 0>; +def : ReadAdvance<ReadFMA64Addend, 0>; def : ReadAdvance<ReadFDiv32, 0>; def : ReadAdvance<ReadFDiv64, 0>; def : ReadAdvance<ReadFSqrt32, 0>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td new file mode 100644 index 000000000000000..da21a311cdf7e00 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td @@ -0,0 +1,307 @@ +//==- RISCVSchedXiangShanNanHu.td - XiangShan-NanHu Scheduling Definitions --*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===-------------------------------------------------------------------------------------===// + +//===-------------------------------------------------------------------------------------===// + +// XiangShan is a high-performance open-source RISC-V processor developed by +// the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences. +// Source: https://github.com/OpenXiangShan/XiangShan +// Documentation: https://github.com/OpenXiangShan/XiangShan-doc + +// XiangShan-NanHu is the second generation of XiangShan processor series. +// Overview: https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/ + +def XiangShanNanHuModel : SchedMachineModel { + let MicroOpBufferSize = 256; + let LoopMicroOpBufferSize = 48; // Instruction queue size + let IssueWidth = 6; // 6-way decode and dispatch + let LoadLatency = 4; + let MispredictPenalty = 11; // Based on estimate of pipeline depth. + let CompleteModel = 0; + let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass. + let UnsupportedFeatures = []; +} + +let SchedModel = XiangShanNanHuModel in { + +// The reservation stations are distributed and grouped as 32-entry or 16-entry smaller ones. +let BufferSize = 16 in { + def XS2ALU : ProcResource<4>; + def XS2MDU : ProcResource<2>; + def XS2MISC : ProcResource<1>; + + def XS2FMAC : ProcResource<4>; + def XS2FMISC : ProcResource<2>; + + // Load/Store queues are ignored. + def XS2LD : ProcResource<2>; + def XS2ST : ProcResource<2>; +} + +// Branching +def : WriteRes<WriteJmp, [XS2MISC]>; +def : WriteRes<WriteJal, [XS2MISC]>; +def : WriteRes<WriteJalr, [XS2MISC]>; + +// Integer arithmetic and logic +let Latency = 1 in { +def : WriteRes<WriteIALU, [XS2ALU]>; +def : WriteRes<WriteIALU32, [XS2ALU]>; +def : WriteRes<WriteShiftImm, [XS2ALU]>; +def : WriteRes<WriteShiftImm32, [XS2ALU]>; +def : WriteRes<WriteShiftReg, [XS2ALU]>; +def : WriteRes<WriteShiftReg32, [XS2ALU]>; +} + +// Integer multiplication +let Latency = 3 in { +def : WriteRes<WriteIMul, [XS2MDU]>; +def : WriteRes<WriteIMul32, [XS2MDU]>; +} + +// Integer division +// SRT16 algorithm +let Latency = 20, ReleaseAtCycles = [20] in { +def : WriteRes<WriteIDiv32, [XS2MDU]>; +def : WriteRes<WriteIDiv, [XS2MDU]>; +} + +// Zb* +let Latency = 1 in { +// Zba +def : WriteRes<WriteSHXADD, [XS2ALU]>; +def : WriteRes<WriteSHXADD32, [XS2ALU]>; + +// Zbb +def : WriteRes<WriteRotateImm, [XS2ALU]>; +def : WriteRes<WriteRotateImm32, [XS2ALU]>; +def : WriteRes<WriteRotateReg, [XS2ALU]>; +def : WriteRes<WriteRotateReg32, [XS2ALU]>; +def : WriteRes<WriteORCB, [XS2ALU]>; +def : WriteRes<WriteREV8, [XS2ALU]>; + +// Zbkb +def : WriteRes<WriteBREV8, [XS2ALU]>; +def : WriteRes<WritePACK, [XS2ALU]>; +def : WriteRes<WritePACK32, [XS2ALU]>; +def : WriteRes<WriteZIP, [XS2ALU]>; +} + +let Latency = 3 in { +// Zbb +def : WriteRes<WriteCLZ, [XS2MDU]>; +def : WriteRes<WriteCLZ32, [XS2MDU]>; +def : WriteRes<WriteCTZ, [XS2MDU]>; +def : WriteRes<WriteCTZ32, [XS2MDU]>; +def : WriteRes<WriteCPOP, [XS2MDU]>; +def : WriteRes<WriteCPOP32, [XS2MDU]>; + +// Zbs +def : WriteRes<WriteSingleBit, [XS2MDU]>; +def : WriteRes<WriteSingleBitImm, [XS2MDU]>; +def : WriteRes<WriteBEXT, [XS2MDU]>; +def : WriteRes<WriteBEXTI, [XS2MDU]>; + +// Zbkc +def : WriteRes<WriteCLMUL, [XS2MDU]>; + +// Zbkx +def : WriteRes<WriteXPERM, [XS2MDU]>; +} + +// Memory +def : WriteRes<WriteSTB, [XS2ST]>; +def : WriteRes<WriteSTH, [XS2ST]>; +def : WriteRes<WriteSTW, [XS2ST]>; +def : WriteRes<WriteSTD, [XS2ST]>; +def : WriteRes<WriteFST32, [XS2ST]>; +def : WriteRes<WriteFST64, [XS2ST]>; +def : WriteRes<WriteAtomicSTW, [XS2ST]>; +def : WriteRes<WriteAtomicSTD, [XS2ST]>; + +let Latency = 5 in { +def : WriteRes<WriteLDB, [XS2LD]>; +def : WriteRes<WriteLDH, [XS2LD]>; +def : WriteRes<WriteLDW, [XS2LD]>; +def : WriteRes<WriteLDD, [XS2LD]>; + +def : WriteRes<WriteAtomicW, [XS2LD]>; +def : WriteRes<WriteAtomicD, [XS2LD]>; +def : WriteRes<WriteAtomicLDW, [XS2LD]>; +def : WriteRes<WriteAtomicLDD, [XS2LD]>; + +def : WriteRes<WriteFLD32, [XS2LD]>; +def : WriteRes<WriteFLD64, [XS2LD]>; +} + +// XiangShan-NanHu uses FuDian FPU instead of Berkeley HardFloat. +// Documentation: https://github.com/OpenXiangShan/fudian + +let Latency = 3 in { +def : WriteRes<WriteFAdd32, [XS2FMAC]>; +def : WriteRes<WriteFSGNJ32, [XS2FMAC]>; +def : WriteRes<WriteFMinMax32, [XS2FMAC]>; +def : WriteRes<WriteFAdd64, [XS2FMAC]>; +def : WriteRes<WriteFSGNJ64, [XS2FMAC]>; +def : WriteRes<WriteFMinMax64, [XS2FMAC]>; + +def : WriteRes<WriteFCvtI32ToF32, [XS2FMAC]>; +def : WriteRes<WriteFCvtI32ToF64, [XS2FMAC]>; +def : WriteRes<WriteFCvtI64ToF32, [XS2FMAC]>; +def : WriteRes<WriteFCvtI64ToF64, [XS2FMAC]>; +def : WriteRes<WriteFCvtF32ToI32, [XS2FMAC]>; +def : WriteRes<WriteFCvtF32ToI64, [XS2FMAC]>; +def : WriteRes<WriteFCvtF64ToI32, [XS2FMAC]>; +def : WriteRes<WriteFCvtF64ToI64, [XS2FMAC]>; +def : WriteRes<WriteFCvtF32ToF64, [XS2FMAC]>; +def : WriteRes<WriteFCvtF64ToF32, [XS2FMAC]>; + +def : WriteRes<WriteFClass32, [XS2FMAC]>; +def : WriteRes<WriteFClass64, [XS2FMAC]>; +def : WriteRes<WriteFCmp32, [XS2FMAC]>; +def : WriteRes<WriteFCmp64, [XS2FMAC]>; +def : WriteRes<WriteFMovF32ToI32, [XS2FMAC]>; +def : WriteRes<WriteFMovI32ToF32, [XS2FMAC]>; +def : WriteRes<WriteFMovF64ToI64, [XS2FMAC]>; +def : WriteRes<WriteFMovI64ToF64, [XS2FMAC]>; +} + +// FP multiplication +let Latency = 3 in { +def : WriteRes<WriteFMul32, [XS2FMAC]>; +def : WriteRes<WriteFMul64, [XS2FMAC]>; +} + +let Latency = 5 in { +def : WriteRes<WriteFMA32, [XS2FMAC]>; +def : WriteRes<WriteFMA64, [XS2FMAC]>; +} + +// FP division +def : WriteRes<WriteFDiv32, [XS2FMISC]> { + let Latency = 11; +} +def : WriteRes<WriteFDiv64, [XS2FMISC]> { + let Latency = 18; +} + +def : WriteRes<WriteFSqrt32, [XS2FMISC]> { + let Latency = 17; +} +def : WriteRes<WriteFSqrt64, [XS2FMISC]> { + let Latency = 31; +} + +// Others +def : WriteRes<WriteCSR, [XS2MISC]>; +def : WriteRes<WriteNop, []>; + +def : InstRW<[WriteIALU], (instrs COPY)>; + +// Bypass and advance + +class XS2LoadToALUBypass<SchedRead read> + : ReadAdvance<read, 1, [WriteLDB, WriteLDH, WriteLDW, WriteLDD, WriteAtomicW, WriteAtomicD, WriteAtomicLDW, WriteAtomicLDD]>; + +def : ReadAdvance<ReadJmp, 0>; +def : ReadAdvance<ReadJalr, 0>; +def : ReadAdvance<ReadCSR, 0>; +def : ReadAdvance<ReadStoreData, 0>; +def : ReadAdvance<ReadMemBase, 0>; +def : XS2LoadToALUBypass<ReadIALU>; +def : XS2LoadToALUBypass<ReadIALU32>; +def : XS2LoadToALUBypass<ReadShiftImm>; +def : XS2LoadToALUBypass<ReadShiftImm32>; +def : XS2LoadToALUBypass<ReadShiftReg>; +def : XS2LoadToALUBypass<ReadShiftReg32>; +def : ReadAdvance<ReadIDiv, 0>; +def : ReadAdvance<ReadIDiv32, 0>; +def : ReadAdvance<ReadIMul, 0>; +def : ReadAdvance<ReadIMul32, 0>; +def : ReadAdvance<ReadAtomicWA, 0>; +def : ReadAdvance<ReadAtomicWD, 0>; +def : ReadAdvance<ReadAtomicDA, 0>; +def : ReadAdvance<ReadAtomicDD, 0>; +def : ReadAdvance<ReadAtomicLDW, 0>; +def : ReadAdvance<ReadAtomicLDD, 0>; +def : ReadAdvance<ReadAtomicSTW, 0>; +def : ReadAdvance<ReadAtomicSTD, 0>; +def : ReadAdvance<ReadFStoreData, 0>; +def : ReadAdvance<ReadFMemBase, 0>; +def : ReadAdvance<ReadFAdd32, 0>; +def : ReadAdvance<ReadFAdd64, 0>; +def : ReadAdvance<ReadFMul32, 0>; +def : ReadAdvance<ReadFMul64, 0>; +def : ReadAdvance<ReadFMA32, 0>; +def : ReadAdvance<ReadFMA32Addend, 2>; // Cascade FMA +def : ReadAdvance<ReadFMA64, 0>; +def : ReadAdvance<ReadFMA64Addend, 2>; // Cascade FMA +def : ReadAdvance<ReadFDiv32, 0>; +def : ReadAdvance<ReadFDiv64, 0>; +def : ReadAdvance<ReadFSqrt32, 0>; +def : ReadAdvance<ReadFSqrt64, 0>; +def : ReadAdvance<ReadFCmp32, 0>; +def : ReadAdvance<ReadFCmp64, 0>; +def : ReadAdvance<ReadFSGNJ32, 0>; +def : ReadAdvance<ReadFSGNJ64, 0>; +def : ReadAdvance<ReadFMinMax32, 0>; +def : ReadAdvance<ReadFMinMax64, 0>; +def : ReadAdvance<ReadFCvtF32ToI32, 0>; +def : ReadAdvance<ReadFCvtF32ToI64, 0>; +def : ReadAdvance<ReadFCvtF64ToI32, 0>; +def : ReadAdvance<ReadFCvtF64ToI64, 0>; +def : ReadAdvance<ReadFCvtI32ToF32, 0>; +def : ReadAdvance<ReadFCvtI32ToF64, 0>; +def : ReadAdvance<ReadFCvtI64ToF32, 0>; +def : ReadAdvance<ReadFCvtI64ToF64, 0>; +def : ReadAdvance<ReadFCvtF32ToF64, 0>; +def : ReadAdvance<ReadFCvtF64ToF32, 0>; +def : ReadAdvance<ReadFMovF32ToI32, 0>; +def : ReadAdvance<ReadFMovI32ToF32, 0>; +def : ReadAdvance<ReadFMovF64ToI64, 0>; +def : ReadAdvance<ReadFMovI64ToF64, 0>; +def : ReadAdvance<ReadFClass32, 0>; +def : ReadAdvance<ReadFClass64, 0>; + +// Zb* +// Zba +def : XS2LoadToALUBypass<ReadSHXADD>; +def : XS2LoadToALUBypass<ReadSHXADD32>; +// Zbb +def : XS2LoadToALUBypass<ReadRotateImm>; +def : XS2LoadToALUBypass<ReadRotateImm32>; +def : XS2LoadToALUBypass<ReadRotateReg>; +def : XS2LoadToALUBypass<ReadRotateReg32>; +def : ReadAdvance<ReadCLZ, 0>; +def : ReadAdvance<ReadCLZ32, 0>; +def : ReadAdvance<ReadCTZ, 0>; +def : ReadAdvance<ReadCTZ32, 0>; +def : ReadAdvance<ReadCPOP, 0>; +def : ReadAdvance<ReadCPOP32, 0>; +def : XS2LoadToALUBypass<ReadORCB>; +def : XS2LoadToALUBypass<ReadREV8>; +// Zbkc +def : ReadAdvance<ReadCLMUL, 0>; +// Zbs +def : ReadAdvance<ReadSingleBit, 0>; +def : ReadAdvance<ReadSingleBitImm, 0>; +// Zbkb +def : XS2LoadToALUBypass<ReadBREV8>; +def : XS2LoadToALUBypass<ReadPACK>; +def : XS2LoadToALUBypass<ReadPACK32>; +def : XS2LoadToALUBypass<ReadZIP>; +// Zbkx +def : ReadAdvance<ReadXPERM, 0>; + +//===----------------------------------------------------------------------===// +// Unsupported extensions +defm : UnsupportedSchedV; +defm : UnsupportedSchedZfa; +defm : UnsupportedSchedZfh; +defm : UnsupportedSchedSFB; +} diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td index af318ea5bf6851a..e42d07a4a4cd3f0 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedule.td +++ b/llvm/lib/Target/RISCV/RISCVSchedule.td @@ -151,7 +151,9 @@ def ReadFMul32 : SchedRead; // 32-bit floating point multiply def ReadFMul64 : SchedRead; // 64-bit floating point multiply def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add +def ReadFMA32Addend : SchedRead; // 32-bit floating point fused multiply-add def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add +def ReadFMA64Addend : SchedRead; // 64-bit floating point fused multiply-add def ReadFDiv16 : SchedRead; // 16-bit floating point d... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/70232 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
