================
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
----------------
ilovepi wrote:
I thought that the scenario was that the platform only supported software, but
the CPU did support the instructions, and would therefore execute
`SSPUSH`/`SSPOPCHK`. I would expect those instructions fail when the memory
region wasn't initialized and the `SSP` register would point to invalid memory.
If that's not what you meant, then I've misunderstood the scenario.
https://github.com/llvm/llvm-project/pull/68075
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
