================
@@ -1249,6 +1249,18 @@ def ProcessorFeatures {
   list<SubtargetFeature> ARLSFeatures =
     !listconcat(SRFFeatures, ARLSAdditionalFeatures);
 
+  // Pantherlake
+  list<SubtargetFeature> PTLAdditionalFeatures = [FeaturePREFETCHI];
+  list<SubtargetFeature> PTLFeatures =
+    !listconcat(ARLSFeatures, PTLAdditionalFeatures);
----------------
FreddyLeaf wrote:

I referred to xed patch: 
https://github.com/intelxed/xed/blob/main/datafiles/ptl/ptl-chips.txt

https://github.com/llvm/llvm-project/pull/69277
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