https://github.com/Leporacanthicus created
https://github.com/llvm/llvm-project/pull/67676
Support for vector scale range arguments, for AArch64 scalable vector extension
(SVE) support.
Adds -msve-vector-bits to the flang frontend, and for flang fc1 the options are
-mvscale-min and -mvscale-max (optional). These match the clang and clang cc1
options for the same purposes.
A further patch will actually USE these arguments.
>From 25b53fa1d6d52e8f22dcd8888aaf5c7fbf47132e Mon Sep 17 00:00:00 2001
From: Mats Petersson <mats.peters...@arm.com>
Date: Fri, 15 Sep 2023 18:52:11 +0100
Subject: [PATCH] [flang]Add vscale argument parsing
Support for vector scale range arguments, for AArch64 scalable vector
extension (SVE) support.
Adds -msve-vector-bits to the flang frontend, and for flang fc1 the
options are -mvscale-min and -mvscale-max (optional). These match the
clang and clang cc1 options for the same purposes.
A further patch will actually USE these arguments.
---
clang/include/clang/Driver/Options.td | 5 ++-
clang/lib/Driver/ToolChains/Flang.cpp | 39 +++++++++++++++++++-
clang/lib/Driver/ToolChains/Flang.h | 7 ++++
flang/include/flang/Frontend/LangOptions.def | 3 ++
flang/lib/Frontend/CompilerInvocation.cpp | 37 +++++++++++++++++++
flang/lib/Frontend/FrontendActions.cpp | 1 +
flang/test/Driver/driver-help-hidden.f90 | 2 +
flang/test/Driver/driver-help.f90 | 4 ++
8 files changed, 95 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index f573f5a06ceb501..4e491f7d76c8622 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4550,18 +4550,19 @@ foreach i = {8-15,18} in
HelpText<"Make the x"#i#" register call-saved (AArch64 only)">;
def msve_vector_bits_EQ : Joined<["-"], "msve-vector-bits=">,
Group<m_aarch64_Features_Group>,
+ Visibility<[ClangOption, FlangOption]>,
HelpText<"Specify the size in bits of an SVE vector register. Defaults to
the"
" vector length agnostic value of \"scalable\". (AArch64 only)">;
} // let Flags = [TargetSpecific]
def mvscale_min_EQ : Joined<["-"], "mvscale-min=">,
Group<m_aarch64_Features_Group>, Flags<[NoXarchOption]>,
- Visibility<[ClangOption, CC1Option]>,
+ Visibility<[ClangOption, CC1Option, FC1Option]>,
HelpText<"Specify the vscale minimum. Defaults to \"1\". (AArch64/RISC-V
only)">,
MarshallingInfoInt<LangOpts<"VScaleMin">>;
def mvscale_max_EQ : Joined<["-"], "mvscale-max=">,
Group<m_aarch64_Features_Group>, Flags<[NoXarchOption]>,
- Visibility<[ClangOption, CC1Option]>,
+ Visibility<[ClangOption, CC1Option, FC1Option]>,
HelpText<"Specify the vscale maximum. Defaults to the"
" vector length agnostic value of \"0\". (AArch64/RISC-V only)">,
MarshallingInfoInt<LangOpts<"VScaleMax">>;
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp
b/clang/lib/Driver/ToolChains/Flang.cpp
index 10f785ce7ab9075..ef18048f2f3203b 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -170,6 +170,39 @@ void Flang::addPicOptions(const ArgList &Args,
ArgStringList &CmdArgs) const {
}
}
+
+void Flang::AddAArch64TargetArgs(const ArgList &Args,
+ ArgStringList &CmdArgs) const {
+ // Handle -msve_vector_bits=<bits>
+ if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits_EQ)) {
+ StringRef Val = A->getValue();
+ const Driver &D = getToolChain().getDriver();
+ if (Val.equals("128") || Val.equals("256") || Val.equals("512") ||
+ Val.equals("1024") || Val.equals("2048") || Val.equals("128+") ||
+ Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") ||
+ Val.equals("2048+")) {
+ unsigned Bits = 0;
+ if (Val.endswith("+"))
+ Val = Val.substr(0, Val.size() - 1);
+ else {
+ bool Invalid = Val.getAsInteger(10, Bits); (void)Invalid;
+ assert(!Invalid && "Failed to parse value");
+ CmdArgs.push_back(
+ Args.MakeArgString("-mvscale-max=" + llvm::Twine(Bits / 128)));
+ }
+
+ bool Invalid = Val.getAsInteger(10, Bits); (void)Invalid;
+ assert(!Invalid && "Failed to parse value");
+ CmdArgs.push_back(
+ Args.MakeArgString("-mvscale-min=" + llvm::Twine(Bits / 128)));
+ // Silently drop requests for vector-length agnostic code as it's implied.
+ } else if (!Val.equals("scalable"))
+ // Handle the unsupported values passed to msve-vector-bits.
+ D.Diag(diag::err_drv_unsupported_option_argument)
+ << A->getSpelling() << Val;
+ }
+}
+
void Flang::addTargetOptions(const ArgList &Args,
ArgStringList &CmdArgs) const {
const ToolChain &TC = getToolChain();
@@ -186,9 +219,13 @@ void Flang::addTargetOptions(const ArgList &Args,
switch (TC.getArch()) {
default:
break;
+ case llvm::Triple::aarch64:
+ getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
+ AddAArch64TargetArgs(Args, CmdArgs);
+ break;
+
case llvm::Triple::r600:
case llvm::Triple::amdgcn:
- case llvm::Triple::aarch64:
case llvm::Triple::riscv64:
case llvm::Triple::x86_64:
getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
diff --git a/clang/lib/Driver/ToolChains/Flang.h
b/clang/lib/Driver/ToolChains/Flang.h
index 962b4ae601726af..0141240b5d3ac90 100644
--- a/clang/lib/Driver/ToolChains/Flang.h
+++ b/clang/lib/Driver/ToolChains/Flang.h
@@ -56,6 +56,13 @@ class LLVM_LIBRARY_VISIBILITY Flang : public Tool {
void addTargetOptions(const llvm::opt::ArgList &Args,
llvm::opt::ArgStringList &CmdArgs) const;
+ /// Add specific options for AArch64 target.
+ ///
+ /// \param [in] Args The list of input driver arguments
+ /// \param [out] CmdArgs The list of output command arguments
+ void AddAArch64TargetArgs(const llvm::opt::ArgList &Args,
+ llvm::opt::ArgStringList &CmdArgs) const;
+
/// Extract offload options from the driver arguments and add them to
/// the command arguments.
/// \param [in] C The current compilation for the driver invocation
diff --git a/flang/include/flang/Frontend/LangOptions.def
b/flang/include/flang/Frontend/LangOptions.def
index b7b244a58253d67..3a1d44f7fb472d1 100644
--- a/flang/include/flang/Frontend/LangOptions.def
+++ b/flang/include/flang/Frontend/LangOptions.def
@@ -53,5 +53,8 @@ LANGOPT(OpenMPNoThreadState, 1, 0)
/// Assume that no thread in a parallel region will encounter a parallel region
LANGOPT(OpenMPNoNestedParallelism, 1, 0)
+LANGOPT(VScaleMin, 32, 0) ///< Minimum vscale range value
+LANGOPT(VScaleMax, 32, 0) ///< Maximum vscale range value
+
#undef LANGOPT
#undef ENUM_LANGOPT
diff --git a/flang/lib/Frontend/CompilerInvocation.cpp
b/flang/lib/Frontend/CompilerInvocation.cpp
index 6c0b90cfac4341d..37315e0e4d27a7a 100644
--- a/flang/lib/Frontend/CompilerInvocation.cpp
+++ b/flang/lib/Frontend/CompilerInvocation.cpp
@@ -986,6 +986,41 @@ static bool parseFloatingPointArgs(CompilerInvocation
&invoc,
return true;
}
+/// Parses vscale range options and populates the CompilerInvocation
+/// accordingly.
+/// Returns false if new errors are generated.
+///
+/// \param [out] invoc Stores the processed arguments
+/// \param [in] args The compiler invocation arguments to parse
+/// \param [out] diags DiagnosticsEngine to report erros with
+static bool parseVScaleArgs(CompilerInvocation &invoc, llvm::opt::ArgList
&args,
+ clang::DiagnosticsEngine &diags) {
+ LangOptions &opts = invoc.getLangOpts();
+ if (const auto arg =
+ args.getLastArg(clang::driver::options::OPT_mvscale_min_EQ)) {
+ llvm::StringRef argValue = llvm::StringRef(arg->getValue());
+ unsigned VScaleMin;
+ if (argValue.getAsInteger(/*Radix=*/10, VScaleMin)) {
+ diags.Report(clang::diag::err_drv_unsupported_option_argument)
+ << arg->getSpelling() << argValue;
+ return false;
+ }
+ opts.VScaleMin = VScaleMin;
+ }
+ if (const auto arg =
+ args.getLastArg(clang::driver::options::OPT_mvscale_max_EQ)) {
+ llvm::StringRef argValue = llvm::StringRef(arg->getValue());
+ unsigned VScaleMax;
+ if (argValue.getAsInteger(/*Radix=w*/ 10, VScaleMax)) {
+ diags.Report(clang::diag::err_drv_unsupported_option_argument)
+ << arg->getSpelling() << argValue;
+ return false;
+ }
+ opts.VScaleMax = VScaleMax;
+ }
+ return true;
+}
+
bool CompilerInvocation::createFromArgs(
CompilerInvocation &res, llvm::ArrayRef<const char *> commandLineArgs,
clang::DiagnosticsEngine &diags, const char *argv0) {
@@ -1079,6 +1114,8 @@ bool CompilerInvocation::createFromArgs(
success &= parseFloatingPointArgs(res, args, diags);
+ success &= parseVScaleArgs(res, args, diags);
+
// Set the string to be used as the return value of the COMPILER_OPTIONS
// intrinsic of iso_fortran_env. This is either passed in from the parent
// compiler driver invocation with an environment variable, or failing that
diff --git a/flang/lib/Frontend/FrontendActions.cpp
b/flang/lib/Frontend/FrontendActions.cpp
index 6cc7808a30d8a0f..e76da33ae03e2e9 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -42,6 +42,7 @@
#include "mlir/Target/LLVMIR/ModuleTranslation.h"
#include "clang/Basic/Diagnostic.h"
#include "clang/Basic/DiagnosticFrontend.h"
+#include "clang/Basic/TargetInfo.h"
#include "clang/Driver/DriverDiagnostic.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
diff --git a/flang/test/Driver/driver-help-hidden.f90
b/flang/test/Driver/driver-help-hidden.f90
index 7aae2b195815e2d..807b0f938d27b5c 100644
--- a/flang/test/Driver/driver-help-hidden.f90
+++ b/flang/test/Driver/driver-help-hidden.f90
@@ -110,6 +110,8 @@
! CHECK-NEXT: -mllvm <value> Additional arguments to forward to
LLVM's option processing
! CHECK-NEXT: -mmlir <value> Additional arguments to forward to
MLIR's option processing
! CHECK-NEXT: -module-dir <dir> Put MODULE files in <dir>
+! CHECK-NEXT: -msve-vector-bits=<value>
+! CHECK-NEXT: Specify the size in bits of an SVE
vector register. Defaults to the vector length agnostic value of "scalable".
(AArch64 only)
! CHECK-NEXT: --no-offload-arch=<value>
! CHECK-NEXT: Remove CUDA/HIP offloading device
architecture (e.g. sm_35, gfx906) from the list of devices to compile for.
'all' resets the list to its default value.
! CHECK-NEXT: -nocpp Disable predefined and command line
preprocessor macros
diff --git a/flang/test/Driver/driver-help.f90
b/flang/test/Driver/driver-help.f90
index 549bec6aca58c1c..4894f90f5310439 100644
--- a/flang/test/Driver/driver-help.f90
+++ b/flang/test/Driver/driver-help.f90
@@ -98,6 +98,8 @@
! HELP-NEXT: -mllvm <value> Additional arguments to forward to LLVM's
option processing
! HELP-NEXT: -mmlir <value> Additional arguments to forward to MLIR's
option processing
! HELP-NEXT: -module-dir <dir> Put MODULE files in <dir>
+! HELP-NEXT: -msve-vector-bits=<value>
+! HELP-NEXT: Specify the size in bits of an SVE
vector register. Defaults to the vector length agnostic value of "scalable".
(AArch64 only)
! HELP-NEXT: --no-offload-arch=<value>
! HELP-NEXT: Remove CUDA/HIP offloading device
architecture (e.g. sm_35, gfx906) from the list of devices to compile for.
'all' resets the list to its default value.
! HELP-NEXT: -nocpp Disable predefined and command line
preprocessor macros
@@ -228,6 +230,8 @@
! HELP-FC1-NEXT: -mreassociate Allow reassociation transformations
for floating-point instructions
! HELP-FC1-NEXT: -mrelocation-model <value>
! HELP-FC1-NEXT: The relocation model to use
+! HELP-FC1-NEXT: -mvscale-max=<value> Specify the vscale maximum. Defaults
to the vector length agnostic value of "0". (AArch64/RISC-V only)
+! HELP-FC1-NEXT: -mvscale-min=<value> Specify the vscale minimum. Defaults
to "1". (AArch64/RISC-V only)
! HELP-FC1-NEXT: -nocpp Disable predefined and command line
preprocessor macros
! HELP-FC1-NEXT: -opt-record-file <value>
! HELP-FC1-NEXT: File name to use for YAML
optimization record output
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