eaeltsin added a comment. This might have another issue with Verilog -
< import "AAA-BBB" foo bar baz --- > import {"AAA-", > "BBB"} foo bar baz I wonder if Verilog allows breaking strings in `import`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154093/new/ https://reviews.llvm.org/D154093 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits