Author: eopXD Date: 2023-07-18T18:57:33-07:00 New Revision: c4a5b58497677f6be2618765f89b08462e820337
URL: https://github.com/llvm/llvm-project/commit/c4a5b58497677f6be2618765f89b08462e820337 DIFF: https://github.com/llvm/llvm-project/commit/c4a5b58497677f6be2618765f89b08462e820337.diff LOG: [Clang][RISCV] Guard RVV intrinsics types that is not available when ELEN < 64 (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at least `zve64x`. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D155414 Added: clang/test/Sema/riscv-vector-zve64x-check.c Modified: clang/include/clang/AST/Type.h clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c Removed: ################################################################################ diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index eea60d7c9831e1..8d20d088bb63c4 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -2306,6 +2306,8 @@ class alignas(8) Type : public ExtQualsTypeCommonBase { /// Check if the type is the CUDA device builtin texture type. bool isCUDADeviceBuiltinTextureType() const; + bool isRVVType(unsigned ElementCount) const; + bool isRVVType() const; bool isRVVType(unsigned Bitwidth, bool IsFloat) const; @@ -7193,6 +7195,16 @@ inline bool Type::isRVVType() const { false; // end of boolean or operation. } +inline bool Type::isRVVType(unsigned ElementCount) const { + bool Ret = false; +#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, \ + IsFP) \ + if (NumEls == ElementCount) \ + Ret |= isSpecificBuiltinType(BuiltinType::Id); +#include "clang/Basic/RISCVVTypes.def" + return Ret; +} + inline bool Type::isRVVType(unsigned Bitwidth, bool IsFloat) const { bool Ret = false; #define RVV_TYPE(Name, Id, SingletonId) diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 339f15ba1217fb..a8bcf498d18da4 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -5331,7 +5331,10 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI, void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { const TargetInfo &TI = Context.getTargetInfo(); - if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) && + // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at + // least zve64x + if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) || + Ty->isRVVType(/* ElementCount */ 1)) && !TI.hasFeature("zve64x")) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x"; if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) && diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c index b07825a831f2da..6eaa175351e3b5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c @@ -6,24 +6,6 @@ #include <riscv_vector.h> -// CHECK-RV64-LABEL: @test_vmulh_vv_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) { - return __riscv_vmulh(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vx_i8mf8(vint8mf8_t op1, int8_t op2, size_t vl) { - return __riscv_vmulh(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i8mf4( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -132,24 +114,6 @@ vint8m8_t test_vmulh_vx_i8m8(vint8m8_t op1, int8_t op2, size_t vl) { return __riscv_vmulh(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vv_i16mf4(vint16mf4_t op1, vint16mf4_t op2, size_t vl) { - return __riscv_vmulh(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vx_i16mf4(vint16mf4_t op1, int16_t op2, size_t vl) { - return __riscv_vmulh(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i16mf2( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -240,24 +204,6 @@ vint16m8_t test_vmulh_vx_i16m8(vint16m8_t op1, int16_t op2, size_t vl) { return __riscv_vmulh(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vv_i32mf2(vint32mf2_t op1, vint32mf2_t op2, size_t vl) { - return __riscv_vmulh(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vx_i32mf2(vint32mf2_t op1, int32_t op2, size_t vl) { - return __riscv_vmulh(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i32m1( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -330,24 +276,6 @@ vint32m8_t test_vmulh_vx_i32m8(vint32m8_t op1, int32_t op2, size_t vl) { return __riscv_vmulh(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vv_i8mf8_m(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { - return __riscv_vmulh(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vx_i8mf8_m(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) { - return __riscv_vmulh(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i8mf4_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -456,24 +384,6 @@ vint8m8_t test_vmulh_vx_i8m8_m(vbool1_t mask, vint8m8_t op1, int8_t op2, size_t return __riscv_vmulh(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vv_i16mf4_m(vbool64_t mask, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { - return __riscv_vmulh(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vx_i16mf4_m(vbool64_t mask, vint16mf4_t op1, int16_t op2, size_t vl) { - return __riscv_vmulh(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i16mf2_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -564,24 +474,6 @@ vint16m8_t test_vmulh_vx_i16m8_m(vbool2_t mask, vint16m8_t op1, int16_t op2, siz return __riscv_vmulh(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vv_i32mf2_m(vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { - return __riscv_vmulh(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vx_i32mf2_m(vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) { - return __riscv_vmulh(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i32m1_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c index 90fb6e6f686674..33f8ac31804baf 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c @@ -6,24 +6,6 @@ #include <riscv_vector.h> -// CHECK-RV64-LABEL: @test_vmulh_vv_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) { - return __riscv_vmulh_vv_i8mf8(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vx_i8mf8(vint8mf8_t op1, int8_t op2, size_t vl) { - return __riscv_vmulh_vx_i8mf8(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i8mf4( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -132,24 +114,6 @@ vint8m8_t test_vmulh_vx_i8m8(vint8m8_t op1, int8_t op2, size_t vl) { return __riscv_vmulh_vx_i8m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vv_i16mf4(vint16mf4_t op1, vint16mf4_t op2, size_t vl) { - return __riscv_vmulh_vv_i16mf4(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vx_i16mf4(vint16mf4_t op1, int16_t op2, size_t vl) { - return __riscv_vmulh_vx_i16mf4(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i16mf2( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -240,24 +204,6 @@ vint16m8_t test_vmulh_vx_i16m8(vint16m8_t op1, int16_t op2, size_t vl) { return __riscv_vmulh_vx_i16m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vv_i32mf2(vint32mf2_t op1, vint32mf2_t op2, size_t vl) { - return __riscv_vmulh_vv_i32mf2(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vx_i32mf2(vint32mf2_t op1, int32_t op2, size_t vl) { - return __riscv_vmulh_vx_i32mf2(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i32m1( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -330,24 +276,6 @@ vint32m8_t test_vmulh_vx_i32m8(vint32m8_t op1, int32_t op2, size_t vl) { return __riscv_vmulh_vx_i32m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vv_i8mf8_m(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { - return __riscv_vmulh_vv_i8mf8_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulh_vx_i8mf8_m(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) { - return __riscv_vmulh_vx_i8mf8_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i8mf4_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -456,24 +384,6 @@ vint8m8_t test_vmulh_vx_i8m8_m(vbool1_t mask, vint8m8_t op1, int8_t op2, size_t return __riscv_vmulh_vx_i8m8_m(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vv_i16mf4_m(vbool64_t mask, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { - return __riscv_vmulh_vv_i16mf4_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulh_vx_i16mf4_m(vbool64_t mask, vint16mf4_t op1, int16_t op2, size_t vl) { - return __riscv_vmulh_vx_i16mf4_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i16mf2_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -564,24 +474,6 @@ vint16m8_t test_vmulh_vx_i16m8_m(vbool2_t mask, vint16m8_t op1, int16_t op2, siz return __riscv_vmulh_vx_i16m8_m(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulh_vv_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vv_i32mf2_m(vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { - return __riscv_vmulh_vv_i32mf2_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulh_vx_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulh_vx_i32mf2_m(vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) { - return __riscv_vmulh_vx_i32mf2_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulh_vv_i32m1_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c index 396611b766b51e..b24f111660afb1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c @@ -6,24 +6,6 @@ #include <riscv_vector.h> -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vv_i8mf8(vint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhsu(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vx_i8mf8(vint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhsu(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf4( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -132,24 +114,6 @@ vint8m8_t test_vmulhsu_vx_i8m8(vint8m8_t op1, uint8_t op2, size_t vl) { return __riscv_vmulhsu(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhsu(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vx_i16mf4(vint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhsu(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf2( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -240,24 +204,6 @@ vint16m8_t test_vmulhsu_vx_i16m8(vint16m8_t op1, uint16_t op2, size_t vl) { return __riscv_vmulhsu(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vv_i32mf2(vint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhsu(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vx_i32mf2(vint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhsu(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i32m1( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -330,24 +276,6 @@ vint32m8_t test_vmulhsu_vx_i32m8(vint32m8_t op1, uint32_t op2, size_t vl) { return __riscv_vmulhsu(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vv_i8mf8_m(vbool64_t mask, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhsu(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vx_i8mf8_m(vbool64_t mask, vint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhsu(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf4_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -456,24 +384,6 @@ vint8m8_t test_vmulhsu_vx_i8m8_m(vbool1_t mask, vint8m8_t op1, uint8_t op2, size return __riscv_vmulhsu(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhsu(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhsu(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf2_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -564,24 +474,6 @@ vint16m8_t test_vmulhsu_vx_i16m8_m(vbool2_t mask, vint16m8_t op1, uint16_t op2, return __riscv_vmulhsu(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhsu(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhsu(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i32m1_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c index 57b3ea32805922..ec092776baf716 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c @@ -6,24 +6,6 @@ #include <riscv_vector.h> -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vv_i8mf8(vint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhsu_vv_i8mf8(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vx_i8mf8(vint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhsu_vx_i8mf8(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf4( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -132,24 +114,6 @@ vint8m8_t test_vmulhsu_vx_i8m8(vint8m8_t op1, uint8_t op2, size_t vl) { return __riscv_vmulhsu_vx_i8m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhsu_vv_i16mf4(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vx_i16mf4(vint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhsu_vx_i16mf4(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf2( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -240,24 +204,6 @@ vint16m8_t test_vmulhsu_vx_i16m8(vint16m8_t op1, uint16_t op2, size_t vl) { return __riscv_vmulhsu_vx_i16m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vv_i32mf2(vint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhsu_vv_i32mf2(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vx_i32mf2(vint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhsu_vx_i32mf2(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i32m1( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -330,24 +276,6 @@ vint32m8_t test_vmulhsu_vx_i32m8(vint32m8_t op1, uint32_t op2, size_t vl) { return __riscv_vmulhsu_vx_i32m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vv_i8mf8_m(vbool64_t mask, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhsu_vv_i8mf8_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vint8mf8_t test_vmulhsu_vx_i8mf8_m(vbool64_t mask, vint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhsu_vx_i8mf8_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i8mf4_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -456,24 +384,6 @@ vint8m8_t test_vmulhsu_vx_i8m8_m(vbool1_t mask, vint8m8_t op1, uint8_t op2, size return __riscv_vmulhsu_vx_i8m8_m(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhsu_vv_i16mf4_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vint16mf4_t test_vmulhsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhsu_vx_i16mf4_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i16mf2_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -564,24 +474,6 @@ vint16m8_t test_vmulhsu_vx_i16m8_m(vbool2_t mask, vint16m8_t op1, uint16_t op2, return __riscv_vmulhsu_vx_i16m8_m(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhsu_vv_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhsu_vv_i32mf2_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhsu_vx_i32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vint32mf2_t test_vmulhsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhsu_vx_i32mf2_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhsu_vv_i32m1_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c index 46cdbca19dbad7..e8a1242912c651 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c @@ -6,24 +6,6 @@ #include <riscv_vector.h> -// CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhu(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vx_u8mf8(vuint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhu(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf4( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -132,24 +114,6 @@ vuint8m8_t test_vmulhu_vx_u8m8(vuint8m8_t op1, uint8_t op2, size_t vl) { return __riscv_vmulhu(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhu(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vx_u16mf4(vuint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhu(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf2( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -240,24 +204,6 @@ vuint16m8_t test_vmulhu_vx_u16m8(vuint16m8_t op1, uint16_t op2, size_t vl) { return __riscv_vmulhu(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhu(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vx_u32mf2(vuint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhu(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u32m1( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -330,24 +276,6 @@ vuint32m8_t test_vmulhu_vx_u32m8(vuint32m8_t op1, uint32_t op2, size_t vl) { return __riscv_vmulhu(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhu(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhu(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf4_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -456,24 +384,6 @@ vuint8m8_t test_vmulhu_vx_u8m8_m(vbool1_t mask, vuint8m8_t op1, uint8_t op2, siz return __riscv_vmulhu(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhu(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhu(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf2_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -564,24 +474,6 @@ vuint16m8_t test_vmulhu_vx_u16m8_m(vbool2_t mask, vuint16m8_t op1, uint16_t op2, return __riscv_vmulhu(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhu(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhu(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u32m1_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c index f84e9170e6813f..811cce25895859 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c @@ -6,24 +6,6 @@ #include <riscv_vector.h> -// CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhu_vv_u8mf8(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u8mf8( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vx_u8mf8(vuint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhu_vx_u8mf8(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf4( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -132,24 +114,6 @@ vuint8m8_t test_vmulhu_vx_u8m8(vuint8m8_t op1, uint8_t op2, size_t vl) { return __riscv_vmulhu_vx_u8m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhu_vv_u16mf4(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u16mf4( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vx_u16mf4(vuint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhu_vx_u16mf4(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf2( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -240,24 +204,6 @@ vuint16m8_t test_vmulhu_vx_u16m8(vuint16m8_t op1, uint16_t op2, size_t vl) { return __riscv_vmulhu_vx_u16m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhu_vv_u32mf2(op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u32mf2( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vx_u32mf2(vuint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhu_vx_u32mf2(op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u32m1( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) @@ -330,24 +276,6 @@ vuint32m8_t test_vmulhu_vx_u32m8(vuint32m8_t op1, uint32_t op2, size_t vl) { return __riscv_vmulhu_vx_u32m8(op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { - return __riscv_vmulhu_vv_u8mf8_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u8mf8_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] -// -vuint8mf8_t test_vmulhu_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) { - return __riscv_vmulhu_vx_u8mf8_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u8mf4_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -456,24 +384,6 @@ vuint8m8_t test_vmulhu_vx_u8m8_m(vbool1_t mask, vuint8m8_t op1, uint8_t op2, siz return __riscv_vmulhu_vx_u8m8_m(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { - return __riscv_vmulhu_vv_u16mf4_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u16mf4_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] -// -vuint16mf4_t test_vmulhu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) { - return __riscv_vmulhu_vx_u16mf4_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u16mf2_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) @@ -564,24 +474,6 @@ vuint16m8_t test_vmulhu_vx_u16m8_m(vbool2_t mask, vuint16m8_t op1, uint16_t op2, return __riscv_vmulhu_vx_u16m8_m(mask, op1, op2, vl); } -// CHECK-RV64-LABEL: @test_vmulhu_vv_u32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { - return __riscv_vmulhu_vv_u32mf2_m(mask, op1, op2, vl); -} - -// CHECK-RV64-LABEL: @test_vmulhu_vx_u32mf2_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) -// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] -// -vuint32mf2_t test_vmulhu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) { - return __riscv_vmulhu_vx_u32mf2_m(mask, op1, op2, vl); -} - // CHECK-RV64-LABEL: @test_vmulhu_vv_u32m1_m( // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3) diff --git a/clang/test/Sema/riscv-vector-zve64x-check.c b/clang/test/Sema/riscv-vector-zve64x-check.c new file mode 100644 index 00000000000000..5fb2ad483f63f2 --- /dev/null +++ b/clang/test/Sema/riscv-vector-zve64x-check.c @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -triple riscv64 \ +// RUN: -target-feature +zve32x -disable-O0-optnone -o - \ +// RUN: -fsyntax-only %s -verify +// REQUIRES: riscv-registered-target + + // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) is not in zve32* + // available when ELEN is smaller than 64. + +__rvv_int8mf8_t foo8() { /* expected-error {{RISC-V type '__rvv_int8mf8_t' requires the 'zve64x' extension}} */ + __rvv_int8mf8_t i8mf8; /* expected-error {{RISC-V type '__rvv_int8mf8_t' requires the 'zve64x' extension}} */ + + (void)i8mf8; /* expected-error {{RISC-V type '__rvv_int8mf8_t' requires the 'zve64x' extension}} */ + + return i8mf8; /* expected-error {{RISC-V type '__rvv_int8mf8_t' requires the 'zve64x' extension}} */ +} + +__rvv_int16mf4_t foo16() { /* expected-error {{RISC-V type '__rvv_int16mf4_t' requires the 'zve64x' extension}} */ + __rvv_int16mf4_t i16mf4; /* expected-error {{RISC-V type '__rvv_int16mf4_t' requires the 'zve64x' extension}} */ + + (void)i16mf4; /* expected-error {{RISC-V type '__rvv_int16mf4_t' requires the 'zve64x' extension}} */ + + return i16mf4; /* expected-error {{RISC-V type '__rvv_int16mf4_t' requires the 'zve64x' extension}} */ +} + +__rvv_int32mf2_t foo32() { /* expected-error {{RISC-V type '__rvv_int32mf2_t' requires the 'zve64x' extension}} */ + __rvv_int32mf2_t i32mf2; /* expected-error {{RISC-V type '__rvv_int32mf2_t' requires the 'zve64x' extension}} */ + + (void)i32mf2; /* expected-error {{RISC-V type '__rvv_int32mf2_t' requires the 'zve64x' extension}} */ + + return i32mf2; /* expected-error {{RISC-V type '__rvv_int32mf2_t' requires the 'zve64x' extension}} */ +} + +__rvv_int64m1_t foo64() { /* expected-error {{RISC-V type '__rvv_int64m1_t' requires the 'zve64x' extension}} */ + __rvv_int64m1_t i64m1; /* expected-error {{RISC-V type '__rvv_int64m1_t' requires the 'zve64x' extension}} */ + + (void)i64m1; /* expected-error {{RISC-V type '__rvv_int64m1_t' requires the 'zve64x' extension}} */ + + return i64m1; /* expected-error {{RISC-V type '__rvv_int64m1_t' requires the 'zve64x' extension}} */ +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
