Author: Craig Topper Date: 2023-07-18T10:04:33-07:00 New Revision: d53d842d12ceb182f1f5c12cc001b09f9000dbf4
URL: https://github.com/llvm/llvm-project/commit/d53d842d12ceb182f1f5c12cc001b09f9000dbf4 DIFF: https://github.com/llvm/llvm-project/commit/d53d842d12ceb182f1f5c12cc001b09f9000dbf4.diff LOG: [RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector. Before falling back to CreateCoercedStore, detect a scalable vector return being coerced to fixed vector. Handle it using a vector.extract intrinsic without going through memory. Reviewed By: c-rhodes Differential Revision: https://reviews.llvm.org/D155495 Added: Modified: clang/lib/CodeGen/CGCall.cpp clang/test/CodeGen/attr-arm-sve-vector-bits-call.c clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c Removed: ################################################################################ diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 90123954b7538f..bd272e016e9267 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -5743,6 +5743,20 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, llvm_unreachable("bad evaluation kind"); } + // If coercing a fixed vector from a scalable vector for ABI + // compatibility, and the types match, use the llvm.vector.extract + // intrinsic to perform the conversion. + if (auto *FixedDst = dyn_cast<llvm::FixedVectorType>(RetIRTy)) { + llvm::Value *V = CI; + if (auto *ScalableSrc = dyn_cast<llvm::ScalableVectorType>(V->getType())) { + if (FixedDst->getElementType() == ScalableSrc->getElementType()) { + llvm::Value *Zero = llvm::Constant::getNullValue(CGM.Int64Ty); + V = Builder.CreateExtractVector(FixedDst, V, Zero, "cast.fixed"); + return RValue::get(V); + } + } + } + Address DestPtr = ReturnValue.getValue(); bool DestIsVolatile = ReturnValue.isVolatile(); diff --git a/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c b/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c index 3d72c1f2b0cd63..6685fe0b27b4f7 100644 --- a/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c +++ b/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c @@ -41,11 +41,7 @@ fixed_int32_t fixed_callee(fixed_int32_t x) { // CHECK-LABEL: @sizeless_caller( // CHECK-NEXT: entry: -// CHECK-NEXT: [[COERCE1:%.*]] = alloca <16 x i32>, align 16 -// CHECK-NEXT: store <vscale x 4 x i32> [[X:%.*]], ptr [[COERCE1]], align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[COERCE1]], align 16, !tbaa [[TBAA6:![0-9]+]] -// CHECK-NEXT: [[CASTSCALABLESVE2:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP1]], i64 0) -// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE2]] +// CHECK-NEXT: ret <vscale x 4 x i32> [[X:%.*]] // svint32_t sizeless_caller(svint32_t x) { return fixed_callee(x); diff --git a/clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c b/clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c index 330e4cd1124e4b..70e1aefe7aaffb 100644 --- a/clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c +++ b/clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c @@ -38,11 +38,7 @@ fixed_int32m1_t fixed_callee(fixed_int32m1_t x) { // CHECK-LABEL: @sizeless_caller( // CHECK-NEXT: entry: -// CHECK-NEXT: [[COERCE1:%.*]] = alloca <8 x i32>, align 8 -// CHECK-NEXT: store <vscale x 2 x i32> [[X:%.*]], ptr [[COERCE1]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[COERCE1]], align 8, !tbaa [[TBAA4:![0-9]+]] -// CHECK-NEXT: [[CASTSCALABLESVE2:%.*]] = tail call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP0]], i64 0) -// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE2]] +// CHECK-NEXT: ret <vscale x 2 x i32> [[X:%.*]] // vint32m1_t sizeless_caller(vint32m1_t x) { return fixed_callee(x); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
