craig.topper updated this revision to Diff 538880.
craig.topper added a comment.
Update __clzl test case to pass an unsigned long instead of signed long.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154910/new/
https://reviews.llvm.org/D154910
Files:
clang/lib/Headers/arm_acle.h
clang/test/CodeGen/arm_acle.c
Index: clang/test/CodeGen/arm_acle.c
===================================================================
--- clang/test/CodeGen/arm_acle.c
+++ clang/test/CodeGen/arm_acle.c
@@ -332,7 +332,7 @@
// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false)
// ARM-NEXT: ret i32 [[TMP0]]
//
-uint32_t test_clz(uint32_t t) {
+unsigned test_clz(uint32_t t) {
return __clz(t);
}
@@ -345,10 +345,9 @@
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1
false)
// AArch64-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
-// AArch64-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64
-// AArch64-NEXT: ret i64 [[CONV_I]]
+// AArch64-NEXT: ret i32 [[CAST_I]]
//
-long test_clzl(long t) {
+unsigned test_clzl(unsigned long t) {
return __clzl(t);
}
@@ -356,10 +355,9 @@
// ARM-NEXT: entry:
// ARM-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)
// ARM-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
-// ARM-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64
-// ARM-NEXT: ret i64 [[CONV_I]]
+// ARM-NEXT: ret i32 [[CAST_I]]
//
-uint64_t test_clzll(uint64_t t) {
+unsigned test_clzll(uint64_t t) {
return __clzll(t);
}
Index: clang/lib/Headers/arm_acle.h
===================================================================
--- clang/lib/Headers/arm_acle.h
+++ clang/lib/Headers/arm_acle.h
@@ -138,28 +138,28 @@
/* CLZ */
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clz(uint32_t __t) {
- return (uint32_t)__builtin_clz(__t);
+ return (unsigned int)__builtin_clz(__t);
}
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clzl(unsigned long __t) {
- return (unsigned long)__builtin_clzl(__t);
+ return (unsigned int)__builtin_clzl(__t);
}
-static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clzll(uint64_t __t) {
- return (uint64_t)__builtin_clzll(__t);
+ return (unsigned int)__builtin_clzll(__t);
}
/* CLS */
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__cls(uint32_t __t) {
return __builtin_arm_cls(__t);
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clsl(unsigned long __t) {
#if __SIZEOF_LONG__ == 4
return __builtin_arm_cls(__t);
@@ -168,7 +168,7 @@
#endif
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clsll(uint64_t __t) {
return __builtin_arm_cls64(__t);
}
Index: clang/test/CodeGen/arm_acle.c
===================================================================
--- clang/test/CodeGen/arm_acle.c
+++ clang/test/CodeGen/arm_acle.c
@@ -332,7 +332,7 @@
// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false)
// ARM-NEXT: ret i32 [[TMP0]]
//
-uint32_t test_clz(uint32_t t) {
+unsigned test_clz(uint32_t t) {
return __clz(t);
}
@@ -345,10 +345,9 @@
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)
// AArch64-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
-// AArch64-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64
-// AArch64-NEXT: ret i64 [[CONV_I]]
+// AArch64-NEXT: ret i32 [[CAST_I]]
//
-long test_clzl(long t) {
+unsigned test_clzl(unsigned long t) {
return __clzl(t);
}
@@ -356,10 +355,9 @@
// ARM-NEXT: entry:
// ARM-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)
// ARM-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
-// ARM-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64
-// ARM-NEXT: ret i64 [[CONV_I]]
+// ARM-NEXT: ret i32 [[CAST_I]]
//
-uint64_t test_clzll(uint64_t t) {
+unsigned test_clzll(uint64_t t) {
return __clzll(t);
}
Index: clang/lib/Headers/arm_acle.h
===================================================================
--- clang/lib/Headers/arm_acle.h
+++ clang/lib/Headers/arm_acle.h
@@ -138,28 +138,28 @@
/* CLZ */
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clz(uint32_t __t) {
- return (uint32_t)__builtin_clz(__t);
+ return (unsigned int)__builtin_clz(__t);
}
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clzl(unsigned long __t) {
- return (unsigned long)__builtin_clzl(__t);
+ return (unsigned int)__builtin_clzl(__t);
}
-static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clzll(uint64_t __t) {
- return (uint64_t)__builtin_clzll(__t);
+ return (unsigned int)__builtin_clzll(__t);
}
/* CLS */
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__cls(uint32_t __t) {
return __builtin_arm_cls(__t);
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clsl(unsigned long __t) {
#if __SIZEOF_LONG__ == 4
return __builtin_arm_cls(__t);
@@ -168,7 +168,7 @@
#endif
}
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clsll(uint64_t __t) {
return __builtin_arm_cls64(__t);
}
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