craig.topper added inline comments.
================
Comment at: clang/lib/AST/ItaniumMangle.cpp:3879
+
+ Out << "9__RVV_VLSI" << 'u' << TypeNameStr.size() << TypeNameStr << "Lj"
<< VecSizeInBits << "EE";
----------------
aaron.ballman wrote:
> CC @rjmccall for ABI review -- naïve, possibly dumb question: shouldn't we be
> using the vendor extended builtin type encoding for this sort of thing?
> (https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangle.builtin-type)
I copied what SVE did and changed to use `__RVV_VLSI` as the name.
Here's the text from ACLE
14.2.6.3.5 C++ mangling of fixed-length SVE types Let VLST be a valid C++ type:
```
VLAT __attribute__((arm_sve_vector_bits(N)))
```
for some SVE vector type or SVE predicate type VLAT. VLST is mangled in the
same way as a template:
```
template<typename, unsigned> struct __SVE_VLS;
with the arguments:
__SVE_VLS<VLAT, N>
```
For example:
```
#if __ARM_FEATURE_SVE_BITS==512
// Mangled as 9__SVE_VLSIu11__SVInt32_tLj512EE
typedef svint32_t vec __attribute__((arm_sve_vector_bits(512)));
// Mangled as 9__SVE_VLSIu10__SVBool_tLj512EE
typedef svbool_t pred __attribute__((arm_sve_vector_bits(512)));
#endif
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153659/new/
https://reviews.llvm.org/D153659
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