garvitgupta08 created this revision.
garvitgupta08 added reviewers: asb, apazos, jrtc27.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck,
luismarques, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX,
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217,
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya,
arichardson.
Herald added a project: All.
garvitgupta08 requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.
Support for below instruction is added
1. CFLUSH.D.L1 <https://reviews.llvm.org/L1>
2. CDISCARD.D.L1 <https://reviews.llvm.org/L1>
3. CEASE
Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.
Spec -
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D153370
Files:
clang/test/Driver/riscv-cpus.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/xsfcie-invalid.s
llvm/test/MC/RISCV/xsfcie-valid.s
Index: llvm/test/MC/RISCV/xsfcie-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-valid.s
@@ -0,0 +1,38 @@
+# SFCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+cflush.d.l1
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+cdiscard.d.l1
+
+# CHECK-INST: cdiscard.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
+
+# CHECK-INST: cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+cease
+
Index: llvm/test/MC/RISCV/xsfcie-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-invalid.s
@@ -0,0 +1,24 @@
+# SFCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76 MC)
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
.attribute arch, "rv32i_zvfbfwma0p6"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv64i_xsfcie"
+# CHECK: attribute 5, "rv64i2p1_xsfcie1p0"
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -142,7 +142,9 @@
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC],
+ FeatureStdExtC,
+ FeatureStdExtZihintpause,
+ FeatureVendorXSfcie],
[TuneSiFive7]>;
def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -504,3 +504,25 @@
}
}
}
+
+let Predicates = [IsRV64, HasVendorXSfcie] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" in {
+def Sfv_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cflush.d.l1","$rs1">, Sched<[]> {
+ let rd = 0;
+ let imm12 = {0b1111,0b1100,0b0000};
+}
+
+def Sfv_CDISCARD_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cdiscard.d.l1","$rs1">, Sched<[]> {
+ let rd = 0;
+ let imm12 = {0b1111,0b1100,0b0010};
+}
+
+def Sfv_CEASE : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "cease","">, Sched<[]> {
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {0b0011,0b0000,0b0101};
+}
+}
+def : InstAlias<"cflush.d.l1", (Sfv_CFLUSH_D_L1 X0)>;
+def : InstAlias<"cdiscard.d.l1", (Sfv_CDISCARD_D_L1 X0)>;
+} // Predicates = [IsRV64, HasVendorXScie]
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -760,6 +760,13 @@
AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
"'XCVbitmanip' (Bit Manipulation)">;
+def FeatureVendorXSfcie
+ : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
+ "'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)">;
+def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
+ AssemblerPredicate<(all_of FeatureVendorXSfcie),
+ "'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)">;
+
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -561,6 +561,8 @@
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
+ "SiFive custom instruction opcode table");
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
return MCDisassembler::Fail;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -132,6 +132,7 @@
{"xtheadsync", RISCVExtensionVersion{1, 0}},
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+ {"xsfcie", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
Index: llvm/docs/ReleaseNotes.rst
===================================================================
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -202,6 +202,8 @@
extension disassembler/assembler.
* Added support for the vendor-defined Xsfvcp (SiFive VCIX) extension
disassembler/assembler.
+* Added support for the vendor-defined Xsfcie (SiFive CIE) extension
+ disassembler/assembler.
* Support for the now-ratified Zawrs extension is no longer experimental.
* Adds support for the vendor-defined XTHeadCmo (cache management operations) extension.
* Adds support for the vendor-defined XTHeadSync (multi-core synchronization instructions) extension.
Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -282,3 +282,6 @@
``XCVbitmanip``
LLVM implements `version 1.3.1 of the Core-V bit manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by Core-V. All instructions are prefixed with `cv.` as described in the specification.
+
+``XSfcie``
+ LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
Index: clang/test/Driver/riscv-cpus.c
===================================================================
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -112,7 +112,8 @@
// MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76"
// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-SIFIVE-S76: "-target-feature" "+c"
-// MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause"
+// MCPU-SIFIVE-S76: "-target-feature" "+xsfcie"
// MCPU-SIFIVE-S76: "-target-abi" "lp64d"
// mcpu with default march
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
