[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

[Alex Bradbury via Phabricator via cfe-commits]

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Now that codegen support for zhinx in landed (D149811 
<https://reviews.llvm.org/D149811>), we should set HasLegalHalfType=true for 
zhinx (see D145071 <https://reviews.llvm.org/D145071> for the patch doing this 
for zfh).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150777

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/Float16-arith.c


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===================================================================
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:    [[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:    [[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:    [[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:    [[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:    [[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:    store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:    [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:    store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:    ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;
 
   return true;



Index: clang/test/CodeGen/RISCV/Float16-arith.c
===================================================================
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:    [[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:    [[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:    [[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:    [[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:    [[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:    store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:    [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:    store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:    ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;
 
   return true;

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