mgabka added inline comments.
================ Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1665 def int_aarch64_sve_mla_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; +def int_aarch64_sve_mla_u : AdvSIMD_Pred3VectorArg_Intrinsic; def int_aarch64_sve_mls : AdvSIMD_Pred3VectorArg_Intrinsic; ---------------- it is not a bug, but just a preference to keep better ordering here, could you move this new definition to be straight below the def int_aarch64_sve_mla ? so the regular and _u intrinsics are defined in the same order as in all other cases. Same request to the mls_u definition. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150553/new/ https://reviews.llvm.org/D150553 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
