dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.
Thanks. LGTM with a few extra suggestions.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14357
+ // Non-mask operands of both Ands should also be in same basic block
+ if (I->getParent() != IA->getParent() ||
+ I->getParent() != IB->getParent())
----------------
I'm not sure if this is necessary, so long as some of the operands can be sunk,
but it is probably OK for the moment to keep as-is.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14361-14363
+ for (unsigned Idx = 0; Idx < MainAnd->getNumOperands(); Idx++) {
+ if (MainAnd->getOperand(Idx) != IA) {
+ Ops.push_back(&MainAnd->getOperandUse(Idx));
----------------
I think this can avoid the loop if we just use
`Ops.push_back(&MainAnd->getOperandUse(MainAnd->getOperand(0) == IA ? 1 : 0));`
================
Comment at: llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll:148
+
+define <4 x i32> @test_bit_sink_operand(<4 x i32> %src, <4 x i32> %dst, <4 x
i32> %mask, i32 %scratch) {
+; CHECK-LABEL: test_bit_sink_operand
----------------
Can you run utils/update_llc_test_checks.py on the file, to generate the
runtime checks? There will be more of them but that should be OK in this case.
It doesn't looks too large.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147266/new/
https://reviews.llvm.org/D147266
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