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Add sifive-x280 processor that uses the SiFive7 scheduler model.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D149710
Files:
clang/test/Driver/riscv-cpus.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVProcessors.td
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@
FeatureStdExtC],
[TuneSiFive7]>;
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+ [Feature64Bit,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtV,
+ FeatureStdExtZvl512b,
+ FeatureStdExtZfh,
+ FeatureStdExtZvfh,
+ FeatureStdExtZba,
+ FeatureStdExtZbb],
+ [TuneSiFive7]>;
+
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model,
[Feature32Bit,
Index: llvm/docs/ReleaseNotes.rst
===================================================================
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -171,6 +171,7 @@
* Updated support experimental vector crypto extensions to version 0.5.1 of
the specification.
* Removed N extension (User-Level Interrupts) CSR names in the assembler.
+* Add sifive-x280 processor.
Changes to the WebAssembly Backend
----------------------------------
Index: clang/test/Driver/riscv-cpus.c
===================================================================
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck
-check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature"
"+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
// Check failed cases
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 |
FileCheck -check-prefix=FAIL-MCPU-NAME %s
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@
FeatureStdExtC],
[TuneSiFive7]>;
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+ [Feature64Bit,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtV,
+ FeatureStdExtZvl512b,
+ FeatureStdExtZfh,
+ FeatureStdExtZvfh,
+ FeatureStdExtZba,
+ FeatureStdExtZbb],
+ [TuneSiFive7]>;
+
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model,
[Feature32Bit,
Index: llvm/docs/ReleaseNotes.rst
===================================================================
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -171,6 +171,7 @@
* Updated support experimental vector crypto extensions to version 0.5.1 of
the specification.
* Removed N extension (User-Level Interrupts) CSR names in the assembler.
+* Add sifive-x280 processor.
Changes to the WebAssembly Backend
----------------------------------
Index: clang/test/Driver/riscv-cpus.c
===================================================================
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
// Check failed cases
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
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