erichkeane added a comment. In D145088#4259209 <https://reviews.llvm.org/D145088#4259209>, @craig.topper wrote:
> In D145088#4259197 <https://reviews.llvm.org/D145088#4259197>, @erichkeane > wrote: > >> has this had an RFC btw? I don't believe I've seen one, and this looks like >> we probably need one. > > It has not had an RFC. It's almost a direct copy of AArch64's implementation, > but changed for RISC-V. Do you know if there was an RFC for AArch64? There was for SVE, is that what you mean? I believe most of that went through extensive RFC. The Sema & before stuff seems fine to me, CodeGen is owned by others, so it'll be up to them. I'm not super up on what RFCs happened/were required for this for AArch64, but I'd suggest we at least have the implementers of the AArch64 implementation review this as well. ================ Comment at: clang/lib/CodeGen/TargetInfo.cpp:11390 + ResType = llvm::ScalableVectorType::get( + llvm::Type::getIntNTy(getVMContext(), XLen), 64 / XLen); + break; ---------------- craig.topper wrote: > jrtc27 wrote: > > erichkeane wrote: > > > craig.topper wrote: > > > > erichkeane wrote: > > > > > Where is 'XLen' from here? > > > > It's a member of RISCVABIInfo. It's 64 for riscv64 triple and 32 for > > > > riscv32 triple. > > > Well, the name is awful :) I'd probably suggest a re-name and hiding it > > > behind a function call (since that way it can be done on the triple, > > > rather than an initialized variable perhaps?), but I'm not really in > > > charge of this target info. > > It's not for anyone in the RISC-V space, since it is defined by the > > architecture and used pervasively (and means the X register LENgth, i.e. > > how many bits in the x0-x31 GPRs). Using anything else in a RISC-V ABI > > context would be worse from a RISC-V perspective. In a random LLVM checkout > > I have I see 1118 instances of `/xlen/i` in llvm/lib/Target/RISCV alone. > It's the term in the RISC-V spec for the size of our integer registers. > Anyone working on RISC-V should be familiar with it. Based on Jessica's post, perhaps it is not an issue. Just was jarring to see something as impenetrable. I'd perhaps suggest something like `XRegisterLen` to make it clear what 'X' is, but just a suggestion for the next folks who are finding their way into contributing patches, despite perhaps not yet being RISCV experts. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145088/new/ https://reviews.llvm.org/D145088 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
