Author: Nikita Popov Date: 2023-02-16T17:05:26+01:00 New Revision: eb3dfa0a248794cc51912705540f1ab1f4dde619
URL: https://github.com/llvm/llvm-project/commit/eb3dfa0a248794cc51912705540f1ab1f4dde619 DIFF: https://github.com/llvm/llvm-project/commit/eb3dfa0a248794cc51912705540f1ab1f4dde619.diff LOG: [Clang] Convert some tests to opaque pointers (NFC) Added: Modified: clang/test/CodeGen/WebAssembly/wasm-varargs.c clang/test/CodeGen/X86/avx512fp16-builtins.c clang/test/CodeGen/X86/ms-x86-intrinsics.c clang/test/CodeGen/ms-intrinsics-other.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/WebAssembly/wasm-varargs.c b/clang/test/CodeGen/WebAssembly/wasm-varargs.c index 869ff4afe5c1..3c743692e094 100644 --- a/clang/test/CodeGen/WebAssembly/wasm-varargs.c +++ b/clang/test/CodeGen/WebAssembly/wasm-varargs.c @@ -1,26 +1,23 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature -// RUN: %clang_cc1 -no-opaque-pointers -triple wasm32-unknown-unknown -o - -emit-llvm %s | FileCheck %s +// RUN: %clang_cc1 -triple wasm32-unknown-unknown -o - -emit-llvm %s | FileCheck %s #include <stdarg.h> // CHECK-LABEL: define {{[^@]+}}@test_i32 -// CHECK-SAME: (i8* noundef [[FMT:%.*]], ...) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 -// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 +// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4 // CHECK-NEXT: [[V:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i8* [[FMT]], i8** [[FMT_ADDR]], align 4 -// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]]) -// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4 -// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 4 -// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[ARGP_CUR]] to i32* -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], i32* [[V]], align 4 -// CHECK-NEXT: [[VA2:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_end(i8* [[VA2]]) -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[V]], align 4 +// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4 +// CHECK-NEXT: call void @llvm.va_start(ptr [[VA]]) +// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4 +// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4 +// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGP_CUR]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[V]], align 4 +// CHECK-NEXT: call void @llvm.va_end(ptr [[VA]]) +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[V]], align 4 // CHECK-NEXT: ret i32 [[TMP2]] // int test_i32(char *fmt, ...) { @@ -35,27 +32,24 @@ int test_i32(char *fmt, ...) { // CHECK-LABEL: define {{[^@]+}}@test_i64 -// CHECK-SAME: (i8* noundef [[FMT:%.*]], ...) #[[ATTR0]] { +// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 -// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 +// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4 // CHECK-NEXT: [[V:%.*]] = alloca i64, align 8 -// CHECK-NEXT: store i8* [[FMT]], i8** [[FMT_ADDR]], align 4 -// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]]) -// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[ARGP_CUR]] to i32 +// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4 +// CHECK-NEXT: call void @llvm.va_start(ptr [[VA]]) +// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARGP_CUR]] to i32 // CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 7 // CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 -// CHECK-NEXT: [[ARGP_CUR_ALIGNED:%.*]] = inttoptr i32 [[TMP2]] to i8* -// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR_ALIGNED]], i32 8 -// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[ARGP_CUR_ALIGNED]] to i64* -// CHECK-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8 -// CHECK-NEXT: store i64 [[TMP4]], i64* [[V]], align 8 -// CHECK-NEXT: [[VA2:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_end(i8* [[VA2]]) -// CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[V]], align 8 +// CHECK-NEXT: [[ARGP_CUR_ALIGNED:%.*]] = inttoptr i32 [[TMP2]] to ptr +// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8 +// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARGP_CUR_ALIGNED]], align 8 +// CHECK-NEXT: store i64 [[TMP4]], ptr [[V]], align 8 +// CHECK-NEXT: call void @llvm.va_end(ptr [[VA]]) +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[V]], align 8 // CHECK-NEXT: ret i64 [[TMP5]] // long long test_i64(char *fmt, ...) { @@ -76,23 +70,18 @@ struct S { }; // CHECK-LABEL: define {{[^@]+}}@test_struct -// CHECK-SAME: (%struct.S* noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], i8* noundef [[FMT:%.*]], ...) #[[ATTR0]] { +// CHECK-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 -// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 -// CHECK-NEXT: store i8* [[FMT]], i8** [[FMT_ADDR]], align 4 -// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]]) -// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4 -// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 4 -// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[ARGP_CUR]] to %struct.S** -// CHECK-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[TMP0]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[AGG_RESULT]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[TMP1]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 12, i1 false) -// CHECK-NEXT: [[VA2:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_end(i8* [[VA2]]) +// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4 +// CHECK-NEXT: call void @llvm.va_start(ptr [[VA]]) +// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4 +// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4 +// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[AGG_RESULT]], ptr align 4 [[TMP1]], i32 12, i1 false) +// CHECK-NEXT: call void @llvm.va_end(ptr [[VA]]) // CHECK-NEXT: ret void // struct S test_struct(char *fmt, ...) { @@ -109,31 +98,23 @@ struct S test_struct(char *fmt, ...) { struct Z {}; // CHECK-LABEL: define {{[^@]+}}@test_empty_struct -// CHECK-SAME: (%struct.S* noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], i8* noundef [[FMT:%.*]], ...) #[[ATTR0]] { +// CHECK-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 -// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 +// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4 // CHECK-NEXT: [[U:%.*]] = alloca [[STRUCT_Z:%.*]], align 1 -// CHECK-NEXT: store i8* [[FMT]], i8** [[FMT_ADDR]], align 4 -// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]]) -// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4 -// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 0 -// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[ARGP_CUR]] to %struct.Z* -// CHECK-NEXT: [[TMP1:%.*]] = bitcast %struct.Z* [[U]] to i8* -// CHECK-NEXT: [[TMP2:%.*]] = bitcast %struct.Z* [[TMP0]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 [[TMP1]], i8* align 4 [[TMP2]], i32 0, i1 false) -// CHECK-NEXT: [[ARGP_CUR2:%.*]] = load i8*, i8** [[VA]], align 4 -// CHECK-NEXT: [[ARGP_NEXT3:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR2]], i32 4 -// CHECK-NEXT: store i8* [[ARGP_NEXT3]], i8** [[VA]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[ARGP_CUR2]] to %struct.S** -// CHECK-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP3]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[AGG_RESULT]] to i8* -// CHECK-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 12, i1 false) -// CHECK-NEXT: [[VA4:%.*]] = bitcast i8** [[VA]] to i8* -// CHECK-NEXT: call void @llvm.va_end(i8* [[VA4]]) +// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4 +// CHECK-NEXT: call void @llvm.va_start(ptr [[VA]]) +// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4 +// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 0 +// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[U]], ptr align 4 [[ARGP_CUR]], i32 0, i1 false) +// CHECK-NEXT: [[ARGP_CUR2:%.*]] = load ptr, ptr [[VA]], align 4 +// CHECK-NEXT: [[ARGP_NEXT3:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR2]], i32 4 +// CHECK-NEXT: store ptr [[ARGP_NEXT3]], ptr [[VA]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGP_CUR2]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[AGG_RESULT]], ptr align 4 [[TMP4]], i32 12, i1 false) +// CHECK-NEXT: call void @llvm.va_end(ptr [[VA]]) // CHECK-NEXT: ret void // struct S test_empty_struct(char *fmt, ...) { diff --git a/clang/test/CodeGen/X86/avx512fp16-builtins.c b/clang/test/CodeGen/X86/avx512fp16-builtins.c index 7bd4b2aac38b..f1049b36f3ce 100644 --- a/clang/test/CodeGen/X86/avx512fp16-builtins.c +++ b/clang/test/CodeGen/X86/avx512fp16-builtins.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding -flax-vector-conversions=none %s -triple=x86_64-unknown-unknown -target-feature +avx512fp16 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -ffreestanding -flax-vector-conversions=none %s -triple=x86_64-unknown-unknown -target-feature +avx512fp16 -emit-llvm -o - -Wall -Werror | FileCheck %s #include <immintrin.h> @@ -83,7 +83,6 @@ __m512h test_mm512_set1_ph(_Float16 h) { __m512h test_mm512_set1_pch(_Float16 _Complex h) { // CHECK-LABEL: @test_mm512_set1_pch - // CHECK: bitcast { half, half }{{.*}} to float // CHECK: insertelement <16 x float> {{.*}}, i32 0 // CHECK: insertelement <16 x float> {{.*}}, i32 1 // CHECK: insertelement <16 x float> {{.*}}, i32 2 @@ -1455,106 +1454,106 @@ __mmask8 test_mm_mask_cmp_sh_mask(__mmask8 __M, __m128h __X, __m128h __Y) { __m128h test_mm_load_sh(void const *A) { // CHECK-LABEL: test_mm_load_sh - // CHECK: load half, half* %{{.*}}, align 1{{$}} + // CHECK: load half, ptr %{{.*}}, align 1{{$}} return _mm_load_sh(A); } __m128h test_mm_mask_load_sh(__m128h __A, __mmask8 __U, const void *__W) { // CHECK-LABEL: @test_mm_mask_load_sh - // CHECK: %{{.*}} = call <8 x half> @llvm.masked.load.v8f16.p0v8f16(<8 x half>* %{{.*}}, i32 1, <8 x i1> %{{.*}}, <8 x half> %{{.*}}) + // CHECK: %{{.*}} = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %{{.*}}, i32 1, <8 x i1> %{{.*}}, <8 x half> %{{.*}}) return _mm_mask_load_sh(__A, __U, __W); } __m128h test_mm_maskz_load_sh(__mmask8 __U, const void *__W) { // CHECK-LABEL: @test_mm_maskz_load_sh - // CHECK: %{{.*}} = call <8 x half> @llvm.masked.load.v8f16.p0v8f16(<8 x half>* %{{.*}}, i32 1, <8 x i1> %{{.*}}, <8 x half> %{{.*}}) + // CHECK: %{{.*}} = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %{{.*}}, i32 1, <8 x i1> %{{.*}}, <8 x half> %{{.*}}) return _mm_maskz_load_sh(__U, __W); } __m512h test_mm512_load_ph(void *p) { // CHECK-LABEL: @test_mm512_load_ph - // CHECK: load <32 x half>, <32 x half>* %{{.*}}, align 64{{$}} + // CHECK: load <32 x half>, ptr %{{.*}}, align 64{{$}} return _mm512_load_ph(p); } __m256h test_mm256_load_ph(void *p) { // CHECK-LABEL: @test_mm256_load_ph - // CHECK: load <16 x half>, <16 x half>* %{{.*}}, align 32{{$}} + // CHECK: load <16 x half>, ptr %{{.*}}, align 32{{$}} return _mm256_load_ph(p); } __m128h test_mm_load_ph(void *p) { // CHECK-LABEL: @test_mm_load_ph - // CHECK: load <8 x half>, <8 x half>* %{{.*}}, align 16{{$}} + // CHECK: load <8 x half>, ptr %{{.*}}, align 16{{$}} return _mm_load_ph(p); } __m512h test_mm512_loadu_ph(void *p) { // CHECK-LABEL: @test_mm512_loadu_ph - // CHECK: load <32 x half>, <32 x half>* {{.*}}, align 1{{$}} + // CHECK: load <32 x half>, ptr {{.*}}, align 1{{$}} return _mm512_loadu_ph(p); } __m256h test_mm256_loadu_ph(void *p) { // CHECK-LABEL: @test_mm256_loadu_ph - // CHECK: load <16 x half>, <16 x half>* {{.*}}, align 1{{$}} + // CHECK: load <16 x half>, ptr {{.*}}, align 1{{$}} return _mm256_loadu_ph(p); } __m128h test_mm_loadu_ph(void *p) { // CHECK-LABEL: @test_mm_loadu_ph - // CHECK: load <8 x half>, <8 x half>* {{.*}}, align 1{{$}} + // CHECK: load <8 x half>, ptr {{.*}}, align 1{{$}} return _mm_loadu_ph(p); } void test_mm_store_sh(void *A, __m128h B) { // CHECK-LABEL: test_mm_store_sh // CHECK: extractelement <8 x half> %{{.*}}, i32 0 - // CHECK: store half %{{.*}}, half* %{{.*}}, align 1{{$}} + // CHECK: store half %{{.*}}, ptr %{{.*}}, align 1{{$}} _mm_store_sh(A, B); } void test_mm_mask_store_sh(void *__P, __mmask8 __U, __m128h __A) { // CHECK-LABEL: @test_mm_mask_store_sh - // CHECK: call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %{{.*}}, <8 x half>* %{{.*}}, i32 1, <8 x i1> %{{.*}}) + // CHECK: call void @llvm.masked.store.v8f16.p0(<8 x half> %{{.*}}, ptr %{{.*}}, i32 1, <8 x i1> %{{.*}}) _mm_mask_store_sh(__P, __U, __A); } void test_mm512_store_ph(void *p, __m512h a) { // CHECK-LABEL: @test_mm512_store_ph - // CHECK: store <32 x half> %{{.*}}, <32 x half>* %{{.*}}, align 64 + // CHECK: store <32 x half> %{{.*}}, ptr %{{.*}}, align 64 _mm512_store_ph(p, a); } void test_mm256_store_ph(void *p, __m256h a) { // CHECK-LABEL: @test_mm256_store_ph - // CHECK: store <16 x half> %{{.*}}, <16 x half>* %{{.*}}, align 32 + // CHECK: store <16 x half> %{{.*}}, ptr %{{.*}}, align 32 _mm256_store_ph(p, a); } void test_mm_store_ph(void *p, __m128h a) { // CHECK-LABEL: @test_mm_store_ph - // CHECK: store <8 x half> %{{.*}}, <8 x half>* %{{.*}}, align 16 + // CHECK: store <8 x half> %{{.*}}, ptr %{{.*}}, align 16 _mm_store_ph(p, a); } void test_mm512_storeu_ph(void *p, __m512h a) { // CHECK-LABEL: @test_mm512_storeu_ph - // CHECK: store <32 x half> %{{.*}}, <32 x half>* %{{.*}}, align 1{{$}} + // CHECK: store <32 x half> %{{.*}}, ptr %{{.*}}, align 1{{$}} // CHECK-NEXT: ret void _mm512_storeu_ph(p, a); } void test_mm256_storeu_ph(void *p, __m256h a) { // CHECK-LABEL: @test_mm256_storeu_ph - // CHECK: store <16 x half> %{{.*}}, <16 x half>* %{{.*}}, align 1{{$}} + // CHECK: store <16 x half> %{{.*}}, ptr %{{.*}}, align 1{{$}} // CHECK-NEXT: ret void _mm256_storeu_ph(p, a); } void test_mm_storeu_ph(void *p, __m128h a) { // CHECK-LABEL: @test_mm_storeu_ph - // CHECK: store <8 x half> %{{.*}}, <8 x half>* %{{.*}}, align 1{{$}} + // CHECK: store <8 x half> %{{.*}}, ptr %{{.*}}, align 1{{$}} // CHECK-NEXT: ret void _mm_storeu_ph(p, a); } diff --git a/clang/test/CodeGen/X86/ms-x86-intrinsics.c b/clang/test/CodeGen/X86/ms-x86-intrinsics.c index 4de64f8ea597..b4b8f5dc0b8c 100644 --- a/clang/test/CodeGen/X86/ms-x86-intrinsics.c +++ b/clang/test/CodeGen/X86/ms-x86-intrinsics.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -no-opaque-pointers -Werror -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ +// RUN: %clang_cc1 -Werror -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ // RUN: -triple i686--windows -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-I386 -// RUN: %clang_cc1 -no-opaque-pointers -Werror -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ +// RUN: %clang_cc1 -Werror -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ // RUN: -triple x86_64--windows -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X64 @@ -13,8 +13,8 @@ char test__readfsbyte(unsigned long Offset) { } // CHECK-I386-LABEL: define dso_local signext i8 @test__readfsbyte(i32 noundef %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 -// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i8 addrspace(257)* -// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i8, i8 addrspace(257)* [[PTR]], align 1 +// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to ptr addrspace(257) +// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i8, ptr addrspace(257) [[PTR]], align 1 // CHECK-I386: ret i8 [[VALUE:%[0-9]+]] short test__readfsword(unsigned long Offset) { @@ -22,8 +22,8 @@ short test__readfsword(unsigned long Offset) { } // CHECK-I386-LABEL: define dso_local signext i16 @test__readfsword(i32 noundef %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 -// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i16 addrspace(257)* -// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i16, i16 addrspace(257)* [[PTR]], align 2 +// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to ptr addrspace(257) +// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i16, ptr addrspace(257) [[PTR]], align 2 // CHECK-I386: ret i16 [[VALUE:%[0-9]+]] long test__readfsdword(unsigned long Offset) { @@ -31,8 +31,8 @@ long test__readfsdword(unsigned long Offset) { } // CHECK-I386-LABEL: define dso_local i32 @test__readfsdword(i32 noundef %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 -// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i32 addrspace(257)* -// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i32, i32 addrspace(257)* [[PTR]], align 4 +// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to ptr addrspace(257) +// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i32, ptr addrspace(257) [[PTR]], align 4 // CHECK-I386: ret i32 [[VALUE:%[0-9]+]] long long test__readfsqword(unsigned long Offset) { @@ -40,8 +40,8 @@ long long test__readfsqword(unsigned long Offset) { } // CHECK-I386-LABEL: define dso_local i64 @test__readfsqword(i32 noundef %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 -// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i64 addrspace(257)* -// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i64, i64 addrspace(257)* [[PTR]], align 8 +// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to ptr addrspace(257) +// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i64, ptr addrspace(257) [[PTR]], align 8 // CHECK-I386: ret i64 [[VALUE:%[0-9]+]] #endif @@ -71,8 +71,8 @@ char test__readgsbyte(unsigned long Offset) { // CHECK-X64-LABEL: define dso_local i8 @test__readgsbyte(i32 noundef %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 -// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i8 addrspace(256)* -// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i8, i8 addrspace(256)* [[PTR]], align 1 +// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to ptr addrspace(256) +// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i8, ptr addrspace(256) [[PTR]], align 1 // CHECK-X64: ret i8 [[VALUE:%[0-9]+]] short test__readgsword(unsigned long Offset) { @@ -81,8 +81,8 @@ short test__readgsword(unsigned long Offset) { // CHECK-X64-LABEL: define dso_local i16 @test__readgsword(i32 noundef %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 -// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i16 addrspace(256)* -// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i16, i16 addrspace(256)* [[PTR]], align 2 +// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to ptr addrspace(256) +// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i16, ptr addrspace(256) [[PTR]], align 2 // CHECK-X64: ret i16 [[VALUE:%[0-9]+]] long test__readgsdword(unsigned long Offset) { @@ -91,8 +91,8 @@ long test__readgsdword(unsigned long Offset) { // CHECK-X64-LABEL: define dso_local i32 @test__readgsdword(i32 noundef %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 -// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i32 addrspace(256)* -// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i32, i32 addrspace(256)* [[PTR]], align 4 +// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to ptr addrspace(256) +// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i32, ptr addrspace(256) [[PTR]], align 4 // CHECK-X64: ret i32 [[VALUE:%[0-9]+]] long long test__readgsqword(unsigned long Offset) { @@ -101,8 +101,8 @@ long long test__readgsqword(unsigned long Offset) { // CHECK-X64-LABEL: define dso_local i64 @test__readgsqword(i32 noundef %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 -// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i64 addrspace(256)* -// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i64, i64 addrspace(256)* [[PTR]], align 8 +// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to ptr addrspace(256) +// CHECK-X64: [[VALUE:%[0-9]+]] = load volatile i64, ptr addrspace(256) [[PTR]], align 8 // CHECK-X64: ret i64 [[VALUE:%[0-9]+]] __int64 test__mulh(__int64 a, __int64 b) { @@ -122,7 +122,7 @@ __int64 test_mul128(__int64 Multiplier, __int64 *HighProduct) { return _mul128(Multiplier, Multiplicand, HighProduct); } -// CHECK-X64-LABEL: define dso_local i64 @test_mul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct) +// CHECK-X64-LABEL: define dso_local i64 @test_mul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, ptr{{[a-z_ ]*}}%HighProduct) // CHECK-X64: = sext i64 %Multiplier to i128 // CHECK-X64: = sext i64 %Multiplicand to i128 // CHECK-X64: = mul nsw i128 % @@ -134,7 +134,7 @@ unsigned __int64 test_umul128(unsigned __int64 Multiplier, unsigned __int64 *HighProduct) { return _umul128(Multiplier, Multiplicand, HighProduct); } -// CHECK-X64-LABEL: define dso_local i64 @test_umul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct) +// CHECK-X64-LABEL: define dso_local i64 @test_umul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, ptr{{[a-z_ ]*}}%HighProduct) // CHECK-X64: = zext i64 %Multiplier to i128 // CHECK-X64: = zext i64 %Multiplicand to i128 // CHECK-X64: = mul nuw i128 % diff --git a/clang/test/CodeGen/ms-intrinsics-other.c b/clang/test/CodeGen/ms-intrinsics-other.c index ceeb7ece4f71..4bb51087b177 100644 --- a/clang/test/CodeGen/ms-intrinsics-other.c +++ b/clang/test/CodeGen/ms-intrinsics-other.c @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ +// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ // RUN: -triple x86_64--darwin -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ +// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ // RUN: -triple x86_64--linux -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ +// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ // RUN: -triple aarch64--darwin -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s --check-prefix=CHECK-ARM-ARM64 -// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ +// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ // RUN: -triple aarch64--darwin -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s --check-prefix=CHECK-ARM -// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ +// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \ // RUN: -triple armv7--darwin -Oz -emit-llvm %s -o - \ // RUN: | FileCheck %s --check-prefix=CHECK-ARM @@ -24,7 +24,7 @@ unsigned char test_BitScanForward(unsigned LONG *Index, unsigned LONG Mask) { return _BitScanForward(Index, Mask); } -// CHECK: define{{.*}}i8 @test_BitScanForward(i32* {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{ +// CHECK: define{{.*}}i8 @test_BitScanForward(ptr {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{ // CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i32 %Mask, 0 // CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]] // CHECK: [[END_LABEL]]: @@ -32,13 +32,13 @@ unsigned char test_BitScanForward(unsigned LONG *Index, unsigned LONG Mask) { // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[INDEX:%[0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %Mask, i1 true) -// CHECK: store i32 [[INDEX]], i32* %Index, align 4 +// CHECK: store i32 [[INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] unsigned char test_BitScanReverse(unsigned LONG *Index, unsigned LONG Mask) { return _BitScanReverse(Index, Mask); } -// CHECK: define{{.*}}i8 @test_BitScanReverse(i32* {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{ +// CHECK: define{{.*}}i8 @test_BitScanReverse(ptr {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{ // CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i32 %Mask, 0 // CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]] // CHECK: [[END_LABEL]]: @@ -47,14 +47,14 @@ unsigned char test_BitScanReverse(unsigned LONG *Index, unsigned LONG Mask) { // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[REVINDEX:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %Mask, i1 true) // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[REVINDEX]], 31 -// CHECK: store i32 [[INDEX]], i32* %Index, align 4 +// CHECK: store i32 [[INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] #if defined(__x86_64__) unsigned char test_BitScanForward64(unsigned LONG *Index, unsigned __int64 Mask) { return _BitScanForward64(Index, Mask); } -// CHECK: define{{.*}}i8 @test_BitScanForward64(i32* {{[a-z_ ]*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{ +// CHECK: define{{.*}}i8 @test_BitScanForward64(ptr {{[a-z_ ]*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{ // CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i64 %Mask, 0 // CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]] // CHECK: [[END_LABEL]]: @@ -63,13 +63,13 @@ unsigned char test_BitScanForward64(unsigned LONG *Index, unsigned __int64 Mask) // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[INDEX:%[0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %Mask, i1 true) // CHECK: [[TRUNC_INDEX:%[0-9]+]] = trunc i64 [[INDEX]] to i32 -// CHECK: store i32 [[TRUNC_INDEX]], i32* %Index, align 4 +// CHECK: store i32 [[TRUNC_INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] unsigned char test_BitScanReverse64(unsigned LONG *Index, unsigned __int64 Mask) { return _BitScanReverse64(Index, Mask); } -// CHECK: define{{.*}}i8 @test_BitScanReverse64(i32* {{[a-z_ ]*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{ +// CHECK: define{{.*}}i8 @test_BitScanReverse64(ptr {{[a-z_ ]*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{ // CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i64 %Mask, 0 // CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]] // CHECK: [[END_LABEL]]: @@ -79,63 +79,63 @@ unsigned char test_BitScanReverse64(unsigned LONG *Index, unsigned __int64 Mask) // CHECK: [[REVINDEX:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %Mask, i1 true) // CHECK: [[TRUNC_REVINDEX:%[0-9]+]] = trunc i64 [[REVINDEX]] to i32 // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63 -// CHECK: store i32 [[INDEX]], i32* %Index, align 4 +// CHECK: store i32 [[INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] #endif LONG test_InterlockedExchange(LONG volatile *value, LONG mask) { return _InterlockedExchange(value, mask); } -// CHECK: define{{.*}}i32 @test_InterlockedExchange(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedExchange(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask seq_cst, align 4 // CHECK: ret i32 [[RESULT:%[0-9]+]] // CHECK: } LONG test_InterlockedExchangeAdd(LONG volatile *value, LONG mask) { return _InterlockedExchangeAdd(value, mask); } -// CHECK: define{{.*}}i32 @test_InterlockedExchangeAdd(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK: [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedExchangeAdd(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask seq_cst, align 4 // CHECK: ret i32 [[RESULT:%[0-9]+]] // CHECK: } LONG test_InterlockedExchangeSub(LONG volatile *value, LONG mask) { return _InterlockedExchangeSub(value, mask); } -// CHECK: define{{.*}}i32 @test_InterlockedExchangeSub(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK: [[RESULT:%[0-9]+]] = atomicrmw sub i32* %value, i32 %mask seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedExchangeSub(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK: [[RESULT:%[0-9]+]] = atomicrmw sub ptr %value, i32 %mask seq_cst, align 4 // CHECK: ret i32 [[RESULT:%[0-9]+]] // CHECK: } LONG test_InterlockedOr(LONG volatile *value, LONG mask) { return _InterlockedOr(value, mask); } -// CHECK: define{{.*}}i32 @test_InterlockedOr(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK: [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedOr(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask seq_cst, align 4 // CHECK: ret i32 [[RESULT:%[0-9]+]] // CHECK: } LONG test_InterlockedXor(LONG volatile *value, LONG mask) { return _InterlockedXor(value, mask); } -// CHECK: define{{.*}}i32 @test_InterlockedXor(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedXor(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask seq_cst, align 4 // CHECK: ret i32 [[RESULT:%[0-9]+]] // CHECK: } LONG test_InterlockedAnd(LONG volatile *value, LONG mask) { return _InterlockedAnd(value, mask); } -// CHECK: define{{.*}}i32 @test_InterlockedAnd(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK: [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedAnd(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask seq_cst, align 4 // CHECK: ret i32 [[RESULT:%[0-9]+]] // CHECK: } LONG test_InterlockedCompareExchange(LONG volatile *Destination, LONG Exchange, LONG Comperand) { return _InterlockedCompareExchange(Destination, Exchange, Comperand); } -// CHECK: define{{.*}}i32 @test_InterlockedCompareExchange(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ -// CHECK: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange seq_cst seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedCompareExchange(ptr{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ +// CHECK: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange seq_cst seq_cst, align 4 // CHECK: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0 // CHECK: ret i32 [[RESULT]] // CHECK: } @@ -143,8 +143,8 @@ LONG test_InterlockedCompareExchange(LONG volatile *Destination, LONG Exchange, LONG test_InterlockedIncrement(LONG volatile *Addend) { return _InterlockedIncrement(Addend); } -// CHECK: define{{.*}}i32 @test_InterlockedIncrement(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedIncrement(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 seq_cst, align 4 // CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1 // CHECK: ret i32 [[RESULT]] // CHECK: } @@ -152,8 +152,8 @@ LONG test_InterlockedIncrement(LONG volatile *Addend) { LONG test_InterlockedDecrement(LONG volatile *Addend) { return _InterlockedDecrement(Addend); } -// CHECK: define{{.*}}i32 @test_InterlockedDecrement(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 seq_cst, align 4 +// CHECK: define{{.*}}i32 @test_InterlockedDecrement(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 seq_cst, align 4 // CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1 // CHECK: ret i32 [[RESULT]] // CHECK: } @@ -211,8 +211,8 @@ LONG test_InterlockedAdd(LONG volatile *Addend, LONG Value) { return _InterlockedAdd(Addend, Value); } -// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAdd(i32*{{[a-z_ ]*}}%Addend, i32 noundef %Value) {{.*}} { -// CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add i32* %Addend, i32 %Value seq_cst, align 4 +// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAdd(ptr{{[a-z_ ]*}}%Addend, i32 noundef %Value) {{.*}} { +// CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %Addend, i32 %Value seq_cst, align 4 // CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i32 %[[OLDVAL:[0-9]+]], %Value // CHECK-ARM-ARM64: ret i32 %[[NEWVAL:[0-9]+]] #endif @@ -221,52 +221,52 @@ LONG test_InterlockedAdd(LONG volatile *Addend, LONG Value) { LONG test_InterlockedExchangeAdd_acq(LONG volatile *value, LONG mask) { return _InterlockedExchangeAdd_acq(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_acq(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask acquire, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedExchangeAdd_rel(LONG volatile *value, LONG mask) { return _InterlockedExchangeAdd_rel(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_rel(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask release, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedExchangeAdd_nf(LONG volatile *value, LONG mask) { return _InterlockedExchangeAdd_nf(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_nf(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask monotonic, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedExchange_acq(LONG volatile *value, LONG mask) { return _InterlockedExchange_acq(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_acq(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask acquire, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedExchange_rel(LONG volatile *value, LONG mask) { return _InterlockedExchange_rel(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_rel(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask release, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedExchange_nf(LONG volatile *value, LONG mask) { return _InterlockedExchange_nf(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_nf(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask monotonic, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedCompareExchange_acq(LONG volatile *Destination, LONG Exchange, LONG Comperand) { return _InterlockedCompareExchange_acq(Destination, Exchange, Comperand); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_acq(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange acquire acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_acq(ptr{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange acquire acquire, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -274,8 +274,8 @@ LONG test_InterlockedCompareExchange_acq(LONG volatile *Destination, LONG Exchan LONG test_InterlockedCompareExchange_rel(LONG volatile *Destination, LONG Exchange, LONG Comperand) { return _InterlockedCompareExchange_rel(Destination, Exchange, Comperand); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_rel(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange release monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_rel(ptr{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange release monotonic, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -283,8 +283,8 @@ LONG test_InterlockedCompareExchange_rel(LONG volatile *Destination, LONG Exchan LONG test_InterlockedCompareExchange_nf(LONG volatile *Destination, LONG Exchange, LONG Comperand) { return _InterlockedCompareExchange_nf(Destination, Exchange, Comperand); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_nf(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange monotonic monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_nf(ptr{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange monotonic monotonic, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -292,72 +292,72 @@ LONG test_InterlockedCompareExchange_nf(LONG volatile *Destination, LONG Exchang LONG test_InterlockedOr_acq(LONG volatile *value, LONG mask) { return _InterlockedOr_acq(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_acq(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask acquire, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedOr_rel(LONG volatile *value, LONG mask) { return _InterlockedOr_rel(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_rel(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask release, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedOr_nf(LONG volatile *value, LONG mask) { return _InterlockedOr_nf(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_nf(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask monotonic, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedXor_acq(LONG volatile *value, LONG mask) { return _InterlockedXor_acq(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_acq(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask acquire, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedXor_rel(LONG volatile *value, LONG mask) { return _InterlockedXor_rel(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_rel(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask release, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedXor_nf(LONG volatile *value, LONG mask) { return _InterlockedXor_nf(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_nf(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask monotonic, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedAnd_acq(LONG volatile *value, LONG mask) { return _InterlockedAnd_acq(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_acq(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask acquire, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedAnd_rel(LONG volatile *value, LONG mask) { return _InterlockedAnd_rel(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_rel(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask release, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } LONG test_InterlockedAnd_nf(LONG volatile *value, LONG mask) { return _InterlockedAnd_nf(value, mask); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ -// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_nf(ptr{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{ +// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask monotonic, align 4 // CHECK-ARM: ret i32 [[RESULT:%[0-9]+]] // CHECK-ARM: } @@ -365,8 +365,8 @@ LONG test_InterlockedAnd_nf(LONG volatile *value, LONG mask) { LONG test_InterlockedIncrement_acq(LONG volatile *Addend) { return _InterlockedIncrement_acq(Addend); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_acq(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_acq(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 acquire, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -374,8 +374,8 @@ LONG test_InterlockedIncrement_acq(LONG volatile *Addend) { LONG test_InterlockedIncrement_rel(LONG volatile *Addend) { return _InterlockedIncrement_rel(Addend); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_rel(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_rel(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 release, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -383,8 +383,8 @@ LONG test_InterlockedIncrement_rel(LONG volatile *Addend) { LONG test_InterlockedIncrement_nf(LONG volatile *Addend) { return _InterlockedIncrement_nf(Addend); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_nf(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_nf(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 monotonic, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -392,8 +392,8 @@ LONG test_InterlockedIncrement_nf(LONG volatile *Addend) { LONG test_InterlockedDecrement_acq(LONG volatile *Addend) { return _InterlockedDecrement_acq(Addend); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_acq(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 acquire, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_acq(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 acquire, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -401,8 +401,8 @@ LONG test_InterlockedDecrement_acq(LONG volatile *Addend) { LONG test_InterlockedDecrement_rel(LONG volatile *Addend) { return _InterlockedDecrement_rel(Addend); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_rel(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 release, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_rel(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 release, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } @@ -410,8 +410,8 @@ LONG test_InterlockedDecrement_rel(LONG volatile *Addend) { LONG test_InterlockedDecrement_nf(LONG volatile *Addend) { return _InterlockedDecrement_nf(Addend); } -// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_nf(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 monotonic, align 4 +// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_nf(ptr{{[a-z_ ]*}}%Addend){{.*}}{ +// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 monotonic, align 4 // CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1 // CHECK-ARM: ret i32 [[RESULT]] // CHECK-ARM: } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
