jrtc27 accepted this revision. jrtc27 added a comment. This revision is now accepted and ready to land.
Personally happy with the concept then, seems consistent and overall helpful, just some nits ================ Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:83-86 + "'zifencei' (ifence)">; +def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, + AssemblerPredicate<(all_of FeatureStdExtZifencei), + "'Zifencei' (ifence)">; ---------------- s/ifence/fence.i/ (or Instruction Fence if you want words) for both these ================ Comment at: llvm/test/CodeGen/RISCV/attributes.ll:103-104 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s +; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s + ---------------- ================ Comment at: llvm/test/CodeGen/RISCV/attributes.ll:153-154 +; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0" +; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0" + ---------------- Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143953/new/ https://reviews.llvm.org/D143953 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
