HazardyKnusperkeks added inline comments.
================
Comment at: clang/lib/Format/WhitespaceManager.cpp:839-846
return Style.AlignConsecutiveAssignments.AlignCompound
? C.Tok->getPrecedence() == prec::Assignment
- : C.Tok->is(tok::equal);
+ : C.Tok->is(tok::equal) ||
+ // In Verilog the '<=' is not a compound assignment,
+ // thus it is aligned even when the AlignCompound
+ // option is not set.
+ (Style.isVerilog() && C.Tok->is(tok::lessequal) &&
----------------
Do you need the extra case, or could you just activate `AlignCompound`?
If you do, can you please add parens, the precedence of `?` and `:` in
combination with `||` is at least for me not 100% clear.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142891/new/
https://reviews.llvm.org/D142891
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