Author: Jojo R Date: 2022-12-26T18:32:42+08:00 New Revision: 1179ef46a34292179d3e7e8570d7342edd2dc27d
URL: https://github.com/llvm/llvm-project/commit/1179ef46a34292179d3e7e8570d7342edd2dc27d DIFF: https://github.com/llvm/llvm-project/commit/1179ef46a34292179d3e7e8570d7342edd2dc27d.diff LOG: [RISCV] Implement assembler support for XTHeadVdot This patch implements the T-Head vendor extensions (XTHeadVdot), which is documented here, it's based on standard vector extension v1.0: https://github.com/T-head-Semi/thead-extension-spec Added: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td llvm/test/MC/RISCV/XTHeadVdot-valid.s Modified: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/TargetParser/RISCVISAInfo.cpp llvm/test/CodeGen/RISCV/attributes.ll Removed: ################################################################################ diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 8884b0989086d..7791703cbbe46 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -446,6 +446,10 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s // CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}} +// RUN: %clang -target riscv64 -march=rv64ixtheadvdot -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s +// CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}} + // RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s // RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index aa39935153973..c5f947a76eb28 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -160,6 +160,9 @@ The current vendor extensions supported are: ``XVentanaCondOps`` LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchai-convention document linked above. These instructions are only available for riscv64 at this time. +``XTHeadVdot`` + LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchai-convention document linked above. + Specification Documents ======================= diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 4a00e5045462b..42cdd755b5b42 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -474,6 +474,15 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return Result; } } + if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) { + LLVM_DEBUG(dbgs() << "Trying T-Head custom opcode table:\n"); + Result = + decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 2ba00bd7b7b72..c94d426fb72e3 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -445,6 +445,14 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()" AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps), "'XVentanaCondOps' (Ventana Conditional Ops)">; +def FeatureVendorXTHeadVdot + : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true", + "'xtheadvdot' (T-Head Vector Extensions for Dot)", + [FeatureStdExtV]>; +def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">, + AssemblerPredicate<(all_of FeatureVendorXTHeadVdot), + "'xtheadvdot' (T-Head Vector Extensions for Dot)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 85c7ecf00cbc9..e7940bc87e3a0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1852,3 +1852,4 @@ include "RISCVInstrInfoZicbo.td" //===----------------------------------------------------------------------===// include "RISCVInstrInfoXVentana.td" +include "RISCVInstrInfoXTHead.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td new file mode 100644 index 0000000000000..e826e1248c3a3 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td @@ -0,0 +1,69 @@ +//===-- RISCVInstrInfoXTHead.td ----------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the vendor extensions defined by T-Head of Alibaba. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// +class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> { + let Inst{26} = 0; + let Opcode = OPC_CUSTOM_0.Value; + let DecoderNamespace = "THeadV"; +} + +class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> { + let Inst{26} = 1; + let Opcode = OPC_CUSTOM_0.Value; + let DecoderNamespace = "THeadV"; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2) +class THVdotALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> + : THInstVdotVV<funct6, opv, (outs VR:$vd), + (ins VR:$vs1, VR:$vs2, VMaskOp:$vm), + opcodestr, "$vd, $vs1, $vs2$vm">; + +// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2) +class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> + : THInstVdotVX<funct6, opv, (outs VR:$vd), + (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), + opcodestr, "$vd, $rs1, $vs2$vm">; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +//===----------------------------------------------------------------------===// +// Combination of instruction classes. +// Use these multiclasses to define instructions more easily. +//===----------------------------------------------------------------------===// +multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> { + def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx">; +} + +multiclass THVdotVMAQA<string opcodestr, bits<6> funct6> { + def _VV : THVdotALUrVV<funct6, OPMVX, opcodestr # ".vv">; + defm "" : THVdotVMAQA_VX<opcodestr, funct6>; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// +let Predicates = [HasVendorXTHeadVdot], + Constraints = "@earlyclobber $vd", + RVVConstraint = WidenV in { +defm THVdotVMAQA : THVdotVMAQA<"th.vmaqa", 0b100000>; +defm THVdotVMAQAU : THVdotVMAQA<"th.vmaqau", 0b100010>; +defm THVdotVMAQASU : THVdotVMAQA<"th.vmaqasu", 0b100100>; +defm THVdotVMAQAUS : THVdotVMAQA_VX<"th.vmaqaus",0b100110>; +} diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 3eb88e54ddb5c..328749b12845c 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -105,6 +105,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"svnapot", RISCVExtensionVersion{1, 0}}, {"svinval", RISCVExtensionVersion{1, 0}}, {"xventanacondops", RISCVExtensionVersion{1, 0}}, + {"xtheadvdot", RISCVExtensionVersion{1, 0}}, }; static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { @@ -784,6 +785,7 @@ static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"}; static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"}; static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; +static const char *ImpliedExtsXTHeadVdot[] = {"v"}; struct ImpliedExtsEntry { StringLiteral Name; @@ -799,6 +801,7 @@ struct ImpliedExtsEntry { // Note: The table needs to be sorted by name. static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"v"}, {ImpliedExtsV}}, + {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}}, {{"zdinx"}, {ImpliedExtsZdinx}}, {{"zfh"}, {ImpliedExtsZfh}}, {{"zfhmin"}, {ImpliedExtsZfhmin}}, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 8301076952f14..dda8d65350658 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -79,6 +79,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s @@ -163,6 +164,7 @@ ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0" ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0" +; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1" ; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70" diff --git a/llvm/test/MC/RISCV/XTHeadVdot-valid.s b/llvm/test/MC/RISCV/XTHeadVdot-valid.s new file mode 100644 index 0000000000000..2e00bd1cac3ee --- /dev/null +++ b/llvm/test/MC/RISCV/XTHeadVdot-valid.s @@ -0,0 +1,93 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvdot %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvdot %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvdot - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvdot %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +th.vmaqau.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x88] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 88 <unknown> + +th.vmaqau.vv v8, v20, v4 +# CHECK-INST: th.vmaqau.vv v8, v20, v4 +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 8a <unknown> + +th.vmaqau.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 8c <unknown> + +th.vmaqau.vx v8, a0, v4 +# CHECK-INST: th.vmaqau.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 8e <unknown> + +th.vmaqa.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x80] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 80 <unknown> + +th.vmaqa.vv v8, v20, v4 +# CHECK-INST: th.vmaqa.vv v8, v20, v4 +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x82] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 82 <unknown> + +th.vmaqa.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x84] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 84 <unknown> + +th.vmaqa.vx v8, a0, v4 +# CHECK-INST: th.vmaqa.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x86] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 86 <unknown> + +th.vmaqasu.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x90] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 90 <unknown> + +th.vmaqasu.vv v8, v20, v4 +# CHECK-INST: th.vmaqasu.vv v8, v20, v4 +# CHECK-ENCODING: [0x0b,0x64,0x4a,0x92] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 4a 92 <unknown> + +th.vmaqasu.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x94] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 94 <unknown> + +th.vmaqasu.vx v8, a0, v4 +# CHECK-INST: th.vmaqasu.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x96] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 96 <unknown> + +th.vmaqaus.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x0b,0x64,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 9c <unknown> + +th.vmaqaus.vx v8, a0, v4 +# CHECK-INST: th.vmaqaus.vx v8, a0, v4 +# CHECK-ENCODING: [0x0b,0x64,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} +# CHECK-UNKNOWN: 0b 64 45 9e <unknown> _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
