fpetrogalli updated this revision to Diff 484283.
fpetrogalli added a comment.
Herald added a subscriber: pengfei.
This update is not based anymore on D137516 <https://reviews.llvm.org/D137516>,
but uses the refactoring of `TargetParser` as part of `LLVMSupport`
into the new component `LLVMTargetPArser` introduced in D137838
<https://reviews.llvm.org/D137838>. NFCI.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137517/new/
https://reviews.llvm.org/D137517
Files:
clang/lib/Basic/CMakeLists.txt
clang/lib/Driver/CMakeLists.txt
llvm/include/llvm/TargetParser/TargetParser.h
llvm/include/llvm/module.modulemap
llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
llvm/lib/Target/AArch64/CMakeLists.txt
llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
llvm/lib/Target/AMDGPU/CMakeLists.txt
llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
llvm/lib/Target/ARM/CMakeLists.txt
llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/X86/MCA/CMakeLists.txt
llvm/lib/TargetParser/CMakeLists.txt
llvm/lib/TargetParser/TargetParser.cpp
llvm/unittests/Support/CMakeLists.txt
llvm/unittests/Target/AMDGPU/CMakeLists.txt
llvm/unittests/TargetParser/CMakeLists.txt
llvm/utils/TableGen/CMakeLists.txt
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
llvm/utils/TableGen/TableGen.cpp
llvm/utils/TableGen/TableGenBackends.h
Index: llvm/utils/TableGen/TableGenBackends.h
===================================================================
--- llvm/utils/TableGen/TableGenBackends.h
+++ llvm/utils/TableGen/TableGenBackends.h
@@ -94,7 +94,7 @@
void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
void EmitDXILOperation(RecordKeeper &RK, raw_ostream &OS);
-
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS);
} // End llvm namespace
#endif
Index: llvm/utils/TableGen/TableGen.cpp
===================================================================
--- llvm/utils/TableGen/TableGen.cpp
+++ llvm/utils/TableGen/TableGen.cpp
@@ -58,6 +58,7 @@
GenDirectivesEnumDecl,
GenDirectivesEnumImpl,
GenDXILOperation,
+ GenRISCVTargetDef,
};
namespace llvm {
@@ -141,8 +142,9 @@
clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
"Generate directive related implementation code"),
clEnumValN(GenDXILOperation, "gen-dxil-operation",
- "Generate DXIL operation information")));
-
+ "Generate DXIL operation information"),
+ clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
+ "Generate the list of CPU for RISCV")));
cl::OptionCategory PrintEnumsCat("Options for -print-enums");
cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
cl::value_desc("class name"),
@@ -278,6 +280,9 @@
case GenDXILOperation:
EmitDXILOperation(Records, OS);
break;
+ case GenRISCVTargetDef:
+ EmitRISCVTargetDef(Records, OS);
+ break;
}
return false;
Index: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
===================================================================
--- /dev/null
+++ llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -0,0 +1,49 @@
+//===- RISCVTargetDefEmitter.cpp - Generate lists of RISCV CPUs -----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits the include file needed by the target
+// parser to parse the RISCV CPUs.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/TableGen/Record.h"
+
+namespace llvm {
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+ const auto &Map = RK.getDefs();
+
+ OS << "#ifndef PROC\n"
+ << "#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)\n"
+ << "#endif\n\n";
+
+ OS << "PROC(INVALID, {\"invalid\"}, FK_INVALID, {\"\"})\n";
+ // Iterate on all definition records.
+ for (auto &Def : Map) {
+ const auto &Record = Def.second;
+ if (Record->isSubClassOf("RISCVProcessorModelPROC"))
+ OS << "PROC(" << Record->getName() << ", "
+ << "{\"" << Record->getValueAsString("Name") << "\"},"
+ << Record->getValueAsString("EnumFeatures") << ", "
+ << "{\"" << Record->getValueAsString("DefaultMarch") << "\"})\n";
+ }
+ OS << "\n#undef PROC\n";
+ OS << "\n";
+ OS << "#ifndef TUNE_PROC\n"
+ << "#define TUNE_PROC(ENUM, NAME)\n"
+ << "#endif\n\n";
+ OS << "TUNE_PROC(GENERIC, \"generic\")\n";
+ for (auto &Def : Map) {
+ const auto &Record = Def.second;
+ if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC"))
+ OS << "TUNE_PROC(" << Record->getName() << ", "
+ << "\"" << Record->getValueAsString("Name") << "\")\n";
+ }
+
+ OS << "\n#undef TUNE_PROC\n";
+}
+} // namespace llvm
Index: llvm/utils/TableGen/CMakeLists.txt
===================================================================
--- llvm/utils/TableGen/CMakeLists.txt
+++ llvm/utils/TableGen/CMakeLists.txt
@@ -60,6 +60,7 @@
X86RecognizableInstr.cpp
WebAssemblyDisassemblerEmitter.cpp
CTagsEmitter.cpp
+ RISCVTargetDefEmitter.cpp
)
target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel)
set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")
Index: llvm/unittests/TargetParser/CMakeLists.txt
===================================================================
--- llvm/unittests/TargetParser/CMakeLists.txt
+++ llvm/unittests/TargetParser/CMakeLists.txt
@@ -11,3 +11,5 @@
)
target_link_libraries(TargetParserTests PRIVATE LLVMTestingSupport)
+
+target_include_directories(TargetParserTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/unittests/Target/AMDGPU/CMakeLists.txt
===================================================================
--- llvm/unittests/Target/AMDGPU/CMakeLists.txt
+++ llvm/unittests/Target/AMDGPU/CMakeLists.txt
@@ -22,3 +22,5 @@
)
set_property(TARGET AMDGPUTests PROPERTY FOLDER "Tests/UnitTests/TargetTests")
+
+target_include_directories(AMDGPUTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/unittests/Support/CMakeLists.txt
===================================================================
--- llvm/unittests/Support/CMakeLists.txt
+++ llvm/unittests/Support/CMakeLists.txt
@@ -136,3 +136,5 @@
endif()
add_subdirectory(CommandLineInit)
+
+target_include_directories(SupportTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/TargetParser/TargetParser.cpp
===================================================================
--- llvm/lib/TargetParser/TargetParser.cpp
+++ llvm/lib/TargetParser/TargetParser.cpp
@@ -266,7 +266,7 @@
constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) \
{NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
-#include "llvm/TargetParser/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
};
bool checkCPUKind(CPUKind Kind, bool IsRV64) {
@@ -279,14 +279,16 @@
if (Kind == CK_INVALID)
return false;
#define TUNE_PROC(ENUM, NAME) if (Kind == CK_##ENUM) return true;
-#include "llvm/TargetParser/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
+#undef TUNE_PROC
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
}
CPUKind parseCPUKind(StringRef CPU) {
return llvm::StringSwitch<CPUKind>(CPU)
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
-#include "llvm/TargetParser/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
+#undef PROC
.Default(CK_INVALID);
}
@@ -294,7 +296,8 @@
return llvm::StringSwitch<CPUKind>(TuneCPU)
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
-#include "llvm/TargetParser/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
+#undef TUNE_PROC
.Default(CK_INVALID);
}
@@ -316,7 +319,8 @@
Values.emplace_back(C.Name);
}
#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
-#include "llvm/TargetParser/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
+#undef TUNE_PROC
}
// Get all features except standard extension feature
Index: llvm/lib/TargetParser/CMakeLists.txt
===================================================================
--- llvm/lib/TargetParser/CMakeLists.txt
+++ llvm/lib/TargetParser/CMakeLists.txt
@@ -1,3 +1,6 @@
+set(LLVM_TARGET_DEFINITIONS ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
+tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/)
+add_public_tablegen_target(RISCVTargetParserTableGen)
add_llvm_component_library(LLVMTargetParser
AArch64TargetParser.cpp
@@ -18,3 +21,6 @@
LINK_COMPONENTS
Support
)
+
+
+target_include_directories(LLVMTargetParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/X86/MCA/CMakeLists.txt
===================================================================
--- llvm/lib/Target/X86/MCA/CMakeLists.txt
+++ llvm/lib/Target/X86/MCA/CMakeLists.txt
@@ -13,3 +13,5 @@
ADD_TO_COMPONENT
X86
)
+
+ target_include_directories(LLVMX86TargetMCA PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -553,91 +553,104 @@
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROC<string n,
+ SchedMachineModel m,
+ list<SubtargetFeature> f,
+ string enum_features,
+ string default_march,
+ list<SubtargetFeature> tunef = []> : ProcessorModel<n, m, f, tunef> {
+ string EnumFeatures = enum_features;
+ string DefaultMarch = default_march;
+}
+
+class RISCVProcessorModelTUNE_PROC<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []> : ProcessorModel<n,m,f,tunef>;
+
+def GENERIC_RV32 : RISCVProcessorModelPROC<"generic-rv32", NoSchedModel, [Feature32Bit], "FK_NONE", "">;
+def GENERIC_RV64 : RISCVProcessorModelPROC<"generic-rv64", NoSchedModel, [Feature64Bit], "FK_64BIT", "">;
// Support generic for compatibility with other targets. The triple will be used
// to change to the appropriate rv32/rv64 version.
def : ProcessorModel<"generic", NoSchedModel, []>;
-def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>;
-def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
-def : ProcessorModel<"rocket", RocketModel, []>;
+def ROCKET_RV32 : RISCVProcessorModelPROC<"rocket-rv32", RocketModel, [Feature32Bit], "FK_NONE", "">;
+def ROCKET_RV64 : RISCVProcessorModelPROC<"rocket-rv64", RocketModel, [Feature64Bit], "FK_64BIT", "">;
+def ROCKET : RISCVProcessorModelTUNE_PROC<"rocket", RocketModel, []>;
-def : ProcessorModel<"sifive-7-series", SiFive7Model, [],
+def SIFIVE_7 : RISCVProcessorModelTUNE_PROC<"sifive-7-series", SiFive7Model, [],
[TuneSiFive7]>;
-def : ProcessorModel<"sifive-e20", RocketModel, [Feature32Bit,
+def SIFIVE_E20 : RISCVProcessorModelPROC<"sifive-e20", RocketModel, [Feature32Bit,
FeatureStdExtM,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_NONE", "rv32imc">;
-def : ProcessorModel<"sifive-e21", RocketModel, [Feature32Bit,
+def SIFIVE_E21 : RISCVProcessorModelPROC<"sifive-e21", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_NONE", "rv32imac">;
-def : ProcessorModel<"sifive-e24", RocketModel, [Feature32Bit,
+def SIFIVE_E24 : RISCVProcessorModelPROC<"sifive-e24", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_NONE", "rv32imafc">;
-def : ProcessorModel<"sifive-e31", RocketModel, [Feature32Bit,
+def SIFIVE_E31 : RISCVProcessorModelPROC<"sifive-e31", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_NONE", "rv32imac">;
-def : ProcessorModel<"sifive-e34", RocketModel, [Feature32Bit,
+def SIFIVE_E34 : RISCVProcessorModelPROC<"sifive-e34", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_NONE", "rv32imafc">;
-def : ProcessorModel<"sifive-e76", SiFive7Model, [Feature32Bit,
+def SIFIVE_E76 : RISCVProcessorModelPROC<"sifive-e76", SiFive7Model, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtC],
- [TuneSiFive7]>;
+ "FK_NONE", "rv32imafc", [TuneSiFive7]>;
-def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
+def SIFIVE_S21 : RISCVProcessorModelPROC<"sifive-s21", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_64BIT", "rv64imac">;
-def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+def SIFIVE_S51 : RISCVProcessorModelPROC<"sifive-s51", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_64BIT", "rv64imac">;
-def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit,
+def SIFIVE_S54 : RISCVProcessorModelPROC<"sifive-s54", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_64BIT", "rv64gc">;
-def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
+def SIFIVE_S76 : RISCVProcessorModelPROC<"sifive-s76", SiFive7Model, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- [TuneSiFive7]>;
+ "FK_64BIT", "rv64gc", [TuneSiFive7]>;
-def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
+def SIFIVE_U54 : RISCVProcessorModelPROC<"sifive-u54", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC]>;
+ FeatureStdExtC], "FK_64BIT", "rv64gc">;
-def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
+def SIFIVE_U74 : RISCVProcessorModelPROC<"sifive-u74", SiFive7Model, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- [TuneSiFive7]>;
+ "FK_64BIT", "rv64gc",[TuneSiFive7] >;
def : ProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model,
[Feature32Bit, FeatureStdExtC],
Index: llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt
+++ llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt
@@ -21,3 +21,5 @@
ADD_TO_COMPONENT
RISCV
)
+
+target_include_directories(LLVMRISCVDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/RISCV/CMakeLists.txt
===================================================================
--- llvm/lib/Target/RISCV/CMakeLists.txt
+++ llvm/lib/Target/RISCV/CMakeLists.txt
@@ -64,8 +64,13 @@
ADD_TO_COMPONENT
RISCV
+
+ DEPENDS
+ LLVMTargetParser
)
+target_include_directories(LLVMRISCVCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
+
add_subdirectory(AsmParser)
add_subdirectory(Disassembler)
add_subdirectory(MCTargetDesc)
Index: llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
===================================================================
--- llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
+++ llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
@@ -26,3 +26,5 @@
ADD_TO_COMPONENT
ARM
)
+
+target_include_directories(LLVMARMDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/ARM/CMakeLists.txt
===================================================================
--- llvm/lib/Target/ARM/CMakeLists.txt
+++ llvm/lib/Target/ARM/CMakeLists.txt
@@ -97,3 +97,5 @@
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)
+
+target_include_directories(LLVMARMCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
===================================================================
--- llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
+++ llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
@@ -13,3 +13,5 @@
ADD_TO_COMPONENT
ARM
)
+
+target_include_directories(LLVMARMAsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
@@ -16,3 +16,5 @@
ADD_TO_COMPONENT
AMDGPU
)
+
+target_include_directories(LLVMAMDGPUUtils PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
@@ -26,3 +26,5 @@
)
add_dependencies(LLVMAMDGPUDesc LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
@@ -16,3 +16,5 @@
)
add_dependencies(LLVMAMDGPUTargetMCA LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUTargetMCA PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AMDGPU/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -194,3 +194,5 @@
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)
+
+target_include_directories(LLVMAMDGPUCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
@@ -15,3 +15,5 @@
)
add_dependencies(LLVMAMDGPUAsmParser LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUAsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AArch64/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AArch64/CMakeLists.txt
+++ llvm/lib/Target/AArch64/CMakeLists.txt
@@ -117,3 +117,5 @@
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)
+
+target_include_directories(LLVMAArch64CodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
+++ llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
@@ -16,3 +16,4 @@
AArch64
)
+target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: llvm/include/llvm/module.modulemap
===================================================================
--- llvm/include/llvm/module.modulemap
+++ llvm/include/llvm/module.modulemap
@@ -417,7 +417,6 @@
textual header "Support/AArch64TargetParser.def"
textual header "Support/ARMTargetParser.def"
textual header "Support/CSKYTargetParser.def"
- textual header "Support/RISCVTargetParser.def"
textual header "Support/TargetOpcodes.def"
textual header "Support/X86TargetParser.def"
textual header "Support/LoongArchTargetParser.def"
Index: llvm/include/llvm/TargetParser/TargetParser.h
===================================================================
--- llvm/include/llvm/TargetParser/TargetParser.h
+++ llvm/include/llvm/TargetParser/TargetParser.h
@@ -163,7 +163,7 @@
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
-#include "RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
};
enum FeatureKind : unsigned {
Index: clang/lib/Driver/CMakeLists.txt
===================================================================
--- clang/lib/Driver/CMakeLists.txt
+++ clang/lib/Driver/CMakeLists.txt
@@ -97,4 +97,6 @@
LINK_LIBS
clangBasic
${system_libs}
- )
+)
+
+target_include_directories(clangDriver PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
Index: clang/lib/Basic/CMakeLists.txt
===================================================================
--- clang/lib/Basic/CMakeLists.txt
+++ clang/lib/Basic/CMakeLists.txt
@@ -116,3 +116,5 @@
PRIVATE
${LLVM_ATOMIC_LIB}
)
+
+target_include_directories(clangBasic PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)
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