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Herald added projects: clang, LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D137517
Files:
clang/lib/Basic/CMakeLists.txt
clang/lib/Driver/CMakeLists.txt
llvm/include/llvm/TargetSupport/RISCVTargetParser.def
llvm/include/llvm/TargetSupport/TargetParser.h
llvm/include/llvm/module.modulemap
llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
llvm/lib/Target/AArch64/CMakeLists.txt
llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
llvm/lib/Target/AMDGPU/CMakeLists.txt
llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
llvm/lib/Target/ARM/CMakeLists.txt
llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/TargetSupport/CMakeLists.txt
llvm/lib/TargetSupport/TargetParser.cpp
llvm/unittests/Support/CMakeLists.txt
llvm/unittests/TargetSupport/CMakeLists.txt
llvm/utils/TableGen/CMakeLists.txt
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
llvm/utils/TableGen/TableGen.cpp
llvm/utils/TableGen/TableGenBackends.h
Index: llvm/utils/TableGen/TableGenBackends.h
===================================================================
--- llvm/utils/TableGen/TableGenBackends.h
+++ llvm/utils/TableGen/TableGenBackends.h
@@ -94,7 +94,7 @@
void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
void EmitDXILOperation(RecordKeeper &RK, raw_ostream &OS);
-
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS);
} // End llvm namespace
#endif
Index: llvm/utils/TableGen/TableGen.cpp
===================================================================
--- llvm/utils/TableGen/TableGen.cpp
+++ llvm/utils/TableGen/TableGen.cpp
@@ -58,6 +58,7 @@
GenDirectivesEnumDecl,
GenDirectivesEnumImpl,
GenDXILOperation,
+ GenRISCVTargetDef,
};
namespace llvm {
@@ -141,8 +142,9 @@
clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
"Generate directive related implementation code"),
clEnumValN(GenDXILOperation, "gen-dxil-operation",
- "Generate DXIL operation information")));
-
+ "Generate DXIL operation information"),
+ clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
+ "Generate the list of CPU for RISCV")));
cl::OptionCategory PrintEnumsCat("Options for -print-enums");
cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
cl::value_desc("class name"),
@@ -278,6 +280,9 @@
case GenDXILOperation:
EmitDXILOperation(Records, OS);
break;
+ case GenRISCVTargetDef:
+ EmitRISCVTargetDef(Records, OS);
+ break;
}
return false;
Index: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
===================================================================
--- /dev/null
+++ llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -0,0 +1,49 @@
+//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits an assembly printer for the current target.
+// Note that this is currently fairly skeletal, but will grow over time.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/TableGen/Record.h"
+
+namespace llvm {
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+ const auto &Map = RK.getDefs();
+
+ OS << "#ifndef PROC\n"
+ << "#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)\n"
+ << "#endif\n\n";
+
+ OS << "PROC(INVALID, {\"invalid\"}, FK_INVALID, {\"\"})\n";
+ // Iterate on all definition records.
+ for (auto &Def : Map) {
+ const auto &Record = Def.second;
+ if (Record->isSubClassOf("RISCVProcessorModelPROC"))
+ OS << "PROC(" << Record->getValueAsString("Enum") << ", "
+ << "{\"" << Record->getValueAsString("Name") << "\"}, "
+ << Record->getValueAsString("EnumFeatures") << ", "
+ << "{\"" << Record->getValueAsString("DefaultMarch") << "\"})\n";
+ }
+ OS << "\n#undef PROC\n";
+ OS << "\n";
+ OS << "#ifndef TUNE_PROC\n"
+ << "#define TUNE_PROC(ENUM, NAME)\n"
+ << "#endif\n\n";
+ OS << "TUNE_PROC(GENERIC, \"generic\")\n";
+ for (auto &Def : Map) {
+ const auto &Record = Def.second;
+ if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC"))
+ OS << "TUNE_PROC(" << Record->getValueAsString("Enum") << ", "
+ << "\"" << Record->getValueAsString("Name") << "\")\n";
+ }
+
+ OS << "\n#undef TUNE_PROC\n";
+}
+} // namespace llvm
Index: llvm/utils/TableGen/CMakeLists.txt
===================================================================
--- llvm/utils/TableGen/CMakeLists.txt
+++ llvm/utils/TableGen/CMakeLists.txt
@@ -60,6 +60,7 @@
X86RecognizableInstr.cpp
WebAssemblyDisassemblerEmitter.cpp
CTagsEmitter.cpp
+ RISCVTargetDefEmitter.cpp
)
target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel)
set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")
Index: llvm/unittests/TargetSupport/CMakeLists.txt
===================================================================
--- llvm/unittests/TargetSupport/CMakeLists.txt
+++ llvm/unittests/TargetSupport/CMakeLists.txt
@@ -7,3 +7,5 @@
)
target_link_libraries(TargetSupportTests PRIVATE LLVMTestingSupport)
+
+target_include_directories(TargetSupportTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/unittests/Support/CMakeLists.txt
===================================================================
--- llvm/unittests/Support/CMakeLists.txt
+++ llvm/unittests/Support/CMakeLists.txt
@@ -137,3 +137,5 @@
endif()
add_subdirectory(CommandLineInit)
+
+target_include_directories(SupportTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/TargetSupport/TargetParser.cpp
===================================================================
--- llvm/lib/TargetSupport/TargetParser.cpp
+++ llvm/lib/TargetSupport/TargetParser.cpp
@@ -266,7 +266,7 @@
constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) \
{NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
-#include "llvm/TargetSupport/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
};
bool checkCPUKind(CPUKind Kind, bool IsRV64) {
@@ -279,14 +279,14 @@
if (Kind == CK_INVALID)
return false;
#define TUNE_PROC(ENUM, NAME) if (Kind == CK_##ENUM) return true;
-#include "llvm/TargetSupport/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
}
CPUKind parseCPUKind(StringRef CPU) {
return llvm::StringSwitch<CPUKind>(CPU)
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
-#include "llvm/TargetSupport/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
.Default(CK_INVALID);
}
@@ -294,7 +294,7 @@
return llvm::StringSwitch<CPUKind>(TuneCPU)
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
-#include "llvm/TargetSupport/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
.Default(CK_INVALID);
}
@@ -316,7 +316,7 @@
Values.emplace_back(C.Name);
}
#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
-#include "llvm/TargetSupport/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
}
// Get all features except standard extension feature
Index: llvm/lib/TargetSupport/CMakeLists.txt
===================================================================
--- llvm/lib/TargetSupport/CMakeLists.txt
+++ llvm/lib/TargetSupport/CMakeLists.txt
@@ -1,5 +1,14 @@
+
+set(LLVM_TARGET_DEFINITIONS ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
+
+tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/)
+
+add_public_tablegen_target(RISCVTargetSupportTableGen)
+
add_llvm_component_library(LLVMTargetSupport
TargetParser.cpp
LINK_COMPONENTS
Support
)
+
+target_include_directories(LLVMTargetSupport PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -506,68 +506,78 @@
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROC<string enum, string enum_features, string default_march> {
+ string Enum = enum;
+ string EnumFeatures = enum_features;
+ string DefaultMarch = default_march;
+}
+
+class RISCVProcessorModelTUNE_PROC<string enum> {
+ string Enum = enum;
+}
+
+def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>, RISCVProcessorModelPROC<"GENERIC_RV32", "FK_NONE", "">;
+def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>, RISCVProcessorModelPROC<"GENERIC_RV64", "FK_64BIT", "">;
// Support generic for compatibility with other targets. The triple will be used
// to change to the appropriate rv32/rv64 version.
def : ProcessorModel<"generic", NoSchedModel, []>;
-def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>;
-def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
-def : ProcessorModel<"rocket", RocketModel, []>;
+def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>, RISCVProcessorModelPROC<"ROCKET_RV32", "FK_NONE", "">;
+def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>, RISCVProcessorModelPROC<"ROCKET_RV64", "FK_64BIT", "">;
+def : ProcessorModel<"rocket", RocketModel, []>, RISCVProcessorModelTUNE_PROC<"ROCKET">;
def : ProcessorModel<"sifive-7-series", SiFive7Model, [],
- [TuneSiFive7]>;
+ [TuneSiFive7]>, RISCVProcessorModelTUNE_PROC<"SIFIVE_7">;
def : ProcessorModel<"sifive-e20", RocketModel, [Feature32Bit,
FeatureStdExtM,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E20", "FK_NONE", "rv32imc">;
def : ProcessorModel<"sifive-e21", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E21", "FK_NONE", "rv32imac">;
def : ProcessorModel<"sifive-e24", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E24", "FK_NONE", "rv32imafc">;
def : ProcessorModel<"sifive-e31", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E31", "FK_NONE", "rv32imac">;
def : ProcessorModel<"sifive-e34", RocketModel, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E34", "FK_NONE", "rv32imafc">;
def : ProcessorModel<"sifive-e76", SiFive7Model, [Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtC],
- [TuneSiFive7]>;
+ [TuneSiFive7]>, RISCVProcessorModelPROC<"SIFIVE_E76", "FK_NONE", "rv32imafc">;
def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_S21", "FK_64BIT", "rv64imac">;
def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_S51", "FK_64BIT", "rv64imac">;
def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_S54", "FK_64BIT", "rv64gc">;
def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
FeatureStdExtM,
@@ -575,14 +585,14 @@
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- [TuneSiFive7]>;
+ [TuneSiFive7]>, RISCVProcessorModelPROC<"SIFIVE_S76", "FK_64BIT", "rv64gc">;
def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC]>;
+ FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_U54", "FK_64BIT", "rv64gc">;
def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
FeatureStdExtM,
@@ -590,7 +600,7 @@
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- [TuneSiFive7]>;
+ [TuneSiFive7]>, RISCVProcessorModelPROC<"SIFIVE_U74", "FK_64BIT", "rv64gc">;
//===----------------------------------------------------------------------===//
// Define the RISC-V target.
Index: llvm/lib/Target/RISCV/CMakeLists.txt
===================================================================
--- llvm/lib/Target/RISCV/CMakeLists.txt
+++ llvm/lib/Target/RISCV/CMakeLists.txt
@@ -15,6 +15,7 @@
tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def)
add_public_tablegen_target(RISCVCommonTableGen)
@@ -69,3 +70,5 @@
add_subdirectory(Disassembler)
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
+
+#target_include_directories(RISCVCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
===================================================================
--- llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
+++ llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
@@ -25,3 +25,5 @@
ADD_TO_COMPONENT
ARM
)
+
+target_include_directories(LLVMARMDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/ARM/CMakeLists.txt
===================================================================
--- llvm/lib/Target/ARM/CMakeLists.txt
+++ llvm/lib/Target/ARM/CMakeLists.txt
@@ -96,3 +96,5 @@
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)
+
+target_include_directories(LLVMARMCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
===================================================================
--- llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
+++ llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
@@ -12,3 +12,5 @@
ADD_TO_COMPONENT
ARM
)
+
+target_include_directories(LLVMARMAsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt
@@ -16,3 +16,5 @@
ADD_TO_COMPONENT
AMDGPU
)
+
+target_include_directories(LLVMAMDGPUUtils PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
@@ -26,3 +26,5 @@
)
add_dependencies(LLVMAMDGPUDesc LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt
@@ -16,3 +16,5 @@
)
add_dependencies(LLVMAMDGPUTargetMCA LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUTargetMCA PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AMDGPU/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -194,3 +194,5 @@
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)
+
+target_include_directories(LLVMAMDGPUCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
+++ llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt
@@ -15,3 +15,5 @@
)
add_dependencies(LLVMAMDGPUAsmParser LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUAsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AArch64/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AArch64/CMakeLists.txt
+++ llvm/lib/Target/AArch64/CMakeLists.txt
@@ -116,3 +116,5 @@
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)
+
+target_include_directories(LLVMAArch64CodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
+++ llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt
@@ -15,3 +15,4 @@
AArch64
)
+target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: llvm/include/llvm/module.modulemap
===================================================================
--- llvm/include/llvm/module.modulemap
+++ llvm/include/llvm/module.modulemap
@@ -416,7 +416,6 @@
textual header "Support/AArch64TargetParser.def"
textual header "Support/ARMTargetParser.def"
textual header "Support/CSKYTargetParser.def"
- textual header "Support/RISCVTargetParser.def"
textual header "Support/TargetOpcodes.def"
textual header "Support/X86TargetParser.def"
}
Index: llvm/include/llvm/TargetSupport/TargetParser.h
===================================================================
--- llvm/include/llvm/TargetSupport/TargetParser.h
+++ llvm/include/llvm/TargetSupport/TargetParser.h
@@ -163,7 +163,7 @@
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
-#include "RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
};
enum FeatureKind : unsigned {
Index: llvm/include/llvm/TargetSupport/RISCVTargetParser.def
===================================================================
--- llvm/include/llvm/TargetSupport/RISCVTargetParser.def
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef PROC
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
-#endif
-
-PROC(INVALID, {"invalid"}, FK_INVALID, {""})
-PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
-PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
-PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
-PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
-PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
-PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
-PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
-PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
-PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"})
-PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
-PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"})
-PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
-PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
-PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
-PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
-PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
-
-#undef PROC
-
-#ifndef TUNE_PROC
-#define TUNE_PROC(ENUM, NAME)
-#endif
-
-TUNE_PROC(GENERIC, "generic")
-TUNE_PROC(ROCKET, "rocket")
-TUNE_PROC(SIFIVE_7, "sifive-7-series")
-
-#undef TUNE_PROC
Index: clang/lib/Driver/CMakeLists.txt
===================================================================
--- clang/lib/Driver/CMakeLists.txt
+++ clang/lib/Driver/CMakeLists.txt
@@ -97,4 +97,6 @@
LINK_LIBS
clangBasic
${system_libs}
- )
+)
+
+target_include_directories(clangDriver PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
Index: clang/lib/Basic/CMakeLists.txt
===================================================================
--- clang/lib/Basic/CMakeLists.txt
+++ clang/lib/Basic/CMakeLists.txt
@@ -116,3 +116,5 @@
PRIVATE
${LLVM_ATOMIC_LIB}
)
+
+target_include_directories(clangBasic PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)
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