dmgreen added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:941
+ "Neoverse V2 ARM processors", [
+ FeaturePostRAScheduler]>;
+
----------------
Please add FeatureFuseAES and FeatureLSLFast.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:1110
+ FeatureMatMulInt8, FeatureNEON,
FeatureSVE2BitPerm,
+ FeatureSVE2, FeatureFP16FML,
FeatureMTE];
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
----------------
HasV9_0aOps implies some of these features already.
================
Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.cpp:213
break;
+ case NeoverseV2:
+ PrefFunctionLogAlignment = 4;
----------------
This can use the same block as NeoverseN2?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D134352/new/
https://reviews.llvm.org/D134352
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