Author: Sanjay Patel Date: 2022-08-31T15:11:48-04:00 New Revision: cdf3de45d282694290011a2949bdcc61cabb47ef
URL: https://github.com/llvm/llvm-project/commit/cdf3de45d282694290011a2949bdcc61cabb47ef DIFF: https://github.com/llvm/llvm-project/commit/cdf3de45d282694290011a2949bdcc61cabb47ef.diff LOG: [CodeGen] fix misnamed "not" operation; NFC Seeing the wrong instruction for this name in IR is confusing. Most of the tests are not even checking a subsequent use of the value, so I just deleted the over-specified CHECKs. Added: Modified: clang/lib/CodeGen/CGExprScalar.cpp clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c clang/test/CodeGen/X86/avx512f-builtins.c Removed: ################################################################################ diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 9def1285fbc1d..a724f8b6afd76 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -2904,7 +2904,7 @@ Value *ScalarExprEmitter::VisitMinus(const UnaryOperator *E, Value *ScalarExprEmitter::VisitUnaryNot(const UnaryOperator *E) { TestAndClearIgnoreResultAssign(); Value *Op = Visit(E->getSubExpr()); - return Builder.CreateNot(Op, "neg"); + return Builder.CreateNot(Op, "not"); } Value *ScalarExprEmitter::VisitUnaryLNot(const UnaryOperator *E) { diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c index 694d2795d335b..312b5fe1894ea 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c @@ -1863,15 +1863,15 @@ vector bool __int128 test_vec_cmpeq_bool_int128(void) { vector bool __int128 test_vec_cmpne_s128(void) { // CHECK-LABEL: @test_vec_cmpne_s128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> - // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> - // CHECK-NEXT: ret <1 x i128> %neg.i + // CHECK-NEXT: %not.i = xor <1 x i128> %4, <i128 -1> + // CHECK-NEXT: ret <1 x i128> %not.i return vec_cmpne(vsi128a, vsi128b); } vector bool __int128 test_vec_cmpne_u128(void) { // CHECK-LABEL: @test_vec_cmpne_u128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> - // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> + // CHECK-NEXT: xor <1 x i128> %4, <i128 -1> // CHECK-NEXT: ret <1 x i128> return vec_cmpne(vui128a, vui128b); } @@ -1879,7 +1879,7 @@ vector bool __int128 test_vec_cmpne_u128(void) { vector bool __int128 test_vec_cmpne_bool_int128(void) { // CHECK-LABEL: @test_vec_cmpne_bool_int128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> - // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> + // CHECK-NEXT: xor <1 x i128> %4, <i128 -1> // CHECK-NEXT: ret <1 x i128> return vec_cmpne(vbi128a, vbi128b); } @@ -1915,7 +1915,7 @@ vector bool __int128 test_vec_cmplt_u128(void) { vector bool __int128 test_vec_cmpge_s128(void) { // CHECK-LABEL: @test_vec_cmpge_s128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> - // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1> + // CHECK-NEXT: xor <1 x i128> %6, <i128 -1> // CHECK-NEXT: ret <1 x i128> return vec_cmpge(vsi128a, vsi128b); } @@ -1923,7 +1923,7 @@ vector bool __int128 test_vec_cmpge_s128(void) { vector bool __int128 test_vec_cmpge_u128(void) { // CHECK-LABEL: @test_vec_cmpge_u128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> - // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1> + // CHECK-NEXT: xor <1 x i128> %6, <i128 -1> // CHECK-NEXT: ret <1 x i128> return vec_cmpge(vui128a, vui128b); } @@ -1931,7 +1931,7 @@ vector bool __int128 test_vec_cmpge_u128(void) { vector bool __int128 test_vec_cmple_s128(void) { // CHECK-LABEL: @test_vec_cmple_s128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> - // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1> + // CHECK-NEXT: xor <1 x i128> %8, <i128 -1> // CHECK-NEXT: ret <1 x i128> return vec_cmple(vsi128a, vsi128b); } @@ -1939,7 +1939,7 @@ vector bool __int128 test_vec_cmple_s128(void) { vector bool __int128 test_vec_cmple_u128(void) { // CHECK-LABEL: @test_vec_cmple_u128( // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> - // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1> + // CHECK-NEXT: xor <1 x i128> %8, <i128 -1> // CHECK-NEXT: ret <1 x i128> return vec_cmple(vui128a, vui128b); } diff --git a/clang/test/CodeGen/X86/avx512f-builtins.c b/clang/test/CodeGen/X86/avx512f-builtins.c index a803bcfff156c..8a0c273415275 100644 --- a/clang/test/CodeGen/X86/avx512f-builtins.c +++ b/clang/test/CodeGen/X86/avx512f-builtins.c @@ -2866,9 +2866,9 @@ __m512i test_mm512_andnot_si512(__m512i __A, __m512i __B) { //CHECK-LABEL: @test_mm512_andnot_si512 //CHECK: load {{.*}}%__A.addr.i, align 64 - //CHECK: %neg.i = xor{{.*}}, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1> + //CHECK: %not.i = xor{{.*}}, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1> //CHECK: load {{.*}}%__B.addr.i, align 64 - //CHECK: and <8 x i64> %neg.i,{{.*}} + //CHECK: and <8 x i64> %not.i,{{.*}} return _mm512_andnot_si512(__A, __B); } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
