sdesmalen added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll:127
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: st1d { z16.d }, p0, [sp]
-; CHECK-NEXT: st1d { z17.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: st1d { z18.d }, p0, [sp, #2, mul vl]
+; CHECK-NEXT: st1d { z2.d }, p0, [sp]
+; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
----------------
I would have expected no asm changes. The test is not equivalent to the
previous code.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131687/new/
https://reviews.llvm.org/D131687
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