alexander-shaposhnikov updated this revision to Diff 452590.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131872/new/
https://reviews.llvm.org/D131872
Files:
clang/test/CodeGenCXX/threadlocal_address.cpp
llvm/include/llvm/IR/Intrinsics.td
llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86.mir
llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86_64.mir
llvm/test/CodeGen/X86/threadlocal_address.ll
llvm/utils/TableGen/CodeGenIntrinsics.h
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/IntrinsicEmitter.cpp
Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
===================================================================
--- llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -700,11 +700,15 @@
unsigned numAttrs = 0;
// The argument attributes are alreadys sorted by argument index.
+ assert(is_sorted(Intrinsic.ArgumentAttributes) &&
+ "Argument attributes are not sorted");
+
unsigned Ai = 0, Ae = Intrinsic.ArgumentAttributes.size();
if (Ae) {
while (Ai != Ae) {
unsigned AttrIdx = Intrinsic.ArgumentAttributes[Ai].Index;
-
+ if (AttrIdx == 0)
+ OS << " // AttrParam0 corresponds to return value.\n";
OS << " const Attribute::AttrKind AttrParam" << AttrIdx << "[]= {";
ListSeparator LS(",");
@@ -721,6 +725,9 @@
case CodeGenIntrinsic::NoUndef:
OS << LS << "Attribute::NoUndef";
break;
+ case CodeGenIntrinsic::NonNull:
+ OS << LS << "Attribute::NonNull";
+ break;
case CodeGenIntrinsic::Returned:
OS << LS << "Attribute::Returned";
break;
@@ -756,7 +763,8 @@
OS << LSV << V;
OS << "};\n";
}
-
+ // AttributeList::ReturnIndex = 0, AttrParam0 corresponds to return
+ // value.
OS << " AS[" << numAttrs++ << "] = AttributeList::get(C, "
<< AttrIdx << ", AttrParam" << AttrIdx;
if (!AllValuesAreZero)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenTarget.cpp
+++ llvm/utils/TableGen/CodeGenTarget.cpp
@@ -893,6 +893,9 @@
} else if (R->isSubClassOf("NoUndef")) {
unsigned ArgNo = R->getValueAsInt("ArgNo");
ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0);
+ } else if (R->isSubClassOf("NonNull")) {
+ unsigned ArgNo = R->getValueAsInt("ArgNo");
+ ArgumentAttributes.emplace_back(ArgNo, NonNull, 0);
} else if (R->isSubClassOf("Returned")) {
unsigned ArgNo = R->getValueAsInt("ArgNo");
ArgumentAttributes.emplace_back(ArgNo, Returned, 0);
Index: llvm/utils/TableGen/CodeGenIntrinsics.h
===================================================================
--- llvm/utils/TableGen/CodeGenIntrinsics.h
+++ llvm/utils/TableGen/CodeGenIntrinsics.h
@@ -154,6 +154,7 @@
NoCapture,
NoAlias,
NoUndef,
+ NonNull,
Returned,
ReadOnly,
WriteOnly,
Index: llvm/test/CodeGen/X86/threadlocal_address.ll
===================================================================
--- llvm/test/CodeGen/X86/threadlocal_address.ll
+++ llvm/test/CodeGen/X86/threadlocal_address.ll
@@ -37,5 +37,5 @@
ret i32 %3
}
-declare ptr @llvm.threadlocal.address(ptr) nounwind readnone willreturn
-declare ptr addrspace(1) @llvm.threadlocal.address.p1(ptr addrspace(1)) nounwind readnone willreturn
+declare nonnull ptr @llvm.threadlocal.address(ptr nonnull) nounwind readnone willreturn
+declare nonnull ptr addrspace(1) @llvm.threadlocal.address.p1(ptr addrspace(1) nonnull) nounwind readnone willreturn
Index: llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86_64.mir
===================================================================
--- llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86_64.mir
+++ llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86_64.mir
@@ -23,7 +23,7 @@
}
; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
- declare ptr @llvm.threadlocal.address.p0(ptr) #0
+ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #0
attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
Index: llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86.mir
===================================================================
--- llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86.mir
+++ llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86.mir
@@ -33,7 +33,7 @@
}
; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
- declare ptr @llvm.threadlocal.address.p0(ptr) #0
+ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #0
attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
Index: llvm/include/llvm/IR/Intrinsics.td
===================================================================
--- llvm/include/llvm/IR/Intrinsics.td
+++ llvm/include/llvm/IR/Intrinsics.td
@@ -84,6 +84,11 @@
int ArgNo = idx.Value;
}
+// NonNull - The specified argument is not null.
+class NonNull<AttrIndex idx> : IntrinsicProperty {
+ int ArgNo = idx.Value;
+}
+
class Align<AttrIndex idx, int align> : IntrinsicProperty {
int ArgNo = idx.Value;
int Align = align;
@@ -1407,7 +1412,7 @@
// Intrinsic to wrap a thread local variable.
def int_threadlocal_address : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [LLVMMatchType<0>],
- [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+ [NonNull<RetIndex>, NonNull<ArgIndex<0>>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
def int_experimental_stepvector : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[], [IntrNoMem]>;
Index: clang/test/CodeGenCXX/threadlocal_address.cpp
===================================================================
--- clang/test/CodeGenCXX/threadlocal_address.cpp
+++ clang/test/CodeGenCXX/threadlocal_address.cpp
@@ -20,11 +20,11 @@
// CHECK-NEXT: %[[RET:.+]] = load i32, ptr %[[IA2]], align 4
// CHECK-NEXT: ret i32 %[[RET]]
//
-// CHECK: declare ptr @llvm.threadlocal.address.p0(ptr) #[[ATTR_NUM:.+]]
+// CHECK: declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #[[ATTR_NUM:.+]]
//
// CHECK-O1-LABEL: @_Z1gv
// CHECK-O1-NEXT: entry:
-// CHECK-O1-NEXT: %[[I_ADDR:.+]] = {{.*}}call ptr @llvm.threadlocal.address.p0(ptr nonnull @i)
+// CHECK-O1-NEXT: %[[I_ADDR:.+]] = {{.*}}call ptr @llvm.threadlocal.address.p0(ptr @i)
// CHECK-O1-NEXT: %[[VAL:.+]] = load i32, ptr %[[I_ADDR]]
// CHECK-O1-NEXT: %[[INC:.+]] = add nsw i32 %[[VAL]], 1
// CHECK-O1-NEXT: store i32 %[[INC]], ptr %[[I_ADDR]]
@@ -56,7 +56,7 @@
//
// CHECK-O1-LABEL: @_Z1fv
// CHECK-O1-NEXT: entry:
-// CHECK-O1-NEXT: %[[J_ADDR:.+]] = {{.*}}call ptr @llvm.threadlocal.address.p0(ptr nonnull @_ZZ1fvE1j)
+// CHECK-O1-NEXT: %[[J_ADDR:.+]] = {{.*}}call ptr @llvm.threadlocal.address.p0(ptr @_ZZ1fvE1j)
// CHECK-O1-NEXT: %[[VAL:.+]] = load i32, ptr %[[J_ADDR]]
// CHECK-O1-NEXT: %[[INC:.+]] = add nsw i32 %[[VAL]], 1
// CHECK-O1-NEXT: store i32 %[[INC]], ptr %[[J_ADDR]]
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