shchenz added inline comments.
================ Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10744 + Store = DAG.getStore( + Op->getOperand(0), DL, + DAG.getNode(ISD::XOR, DL, VT, Load, DAG.getAllOnesConstant(DL, VT)), ---------------- Nit: Maybe we need to set the chain input for store as the chain output of the load. `Op->getOperand(0)` -> `Load->getValue(1)` There is data dependency between the load and the store, so above change will not impact the correctness. But that makes more sense from memory access order part. ================ Comment at: llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll:190 +; CHECK-FAST-NEXT: addi r4, r1, 120 +; CHECK-FAST-NEXT: stdx r3, r4, r5 +; CHECK-FAST-NEXT: ld r3, -28688(r13) ---------------- We may need to check why we are not storing `not r3, r3` directly to `120(r1)` at -O0, like `std r3, 120(r1)`. Seems now we are storing to `119(r1)` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129016/new/ https://reviews.llvm.org/D129016 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
