lattner accepted this revision.
lattner added a comment.
This revision is now accepted and ready to land.
nice cleanup!
================
Comment at: llvm/lib/Analysis/ConstantFolding.cpp:2884
if (IntrinsicID == Intrinsic::smul_fix_sat) {
- APInt Max = APInt::getSignedMaxValue(Width).sextOrSelf(ExtendedWidth);
- APInt Min = APInt::getSignedMinValue(Width).sextOrSelf(ExtendedWidth);
+ APInt Max = APInt::getSignedMaxValue(Width).sext(ExtendedWidth);
+ APInt Min = APInt::getSignedMinValue(Width).sext(ExtendedWidth);
----------------
I think this can be a zext given the top bit will be zero
================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp:138
- const APInt ConstValue = Const->Value.sextOrSelf(Ty.getSizeInBits());
+ const APInt ConstValue = Const->Value.sext(Ty.getSizeInBits());
// The following code is ported from AArch64ISelLowering.
----------------
plz drop the extraneous 'const' while here.
================
Comment at: llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp:1220
if (Cmp & Comparison::U) {
- const APInt Zx1 = A1.zextOrSelf(MaxW);
- const APInt Zx2 = A2.zextOrSelf(MaxW);
+ const APInt Zx1 = A1.zext(MaxW);
+ const APInt Zx2 = A2.zext(MaxW);
----------------
Here too :)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D125557/new/
https://reviews.llvm.org/D125557
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