peterwaller-arm added inline comments.
================ Comment at: llvm/test/CodeGen/AArch64/zero-call-used-regs.ll:259-262 +; SVE-NEXT: pfalse p0.b +; SVE-NEXT: pfalse p1.b +; SVE-NEXT: pfalse p2.b +; SVE-NEXT: pfalse p3.b ---------------- nickdesaulniers wrote: > N00b question about SVE: do we need `pfalse` for each of the numbered p > registers corresponding to the x registers we zeroed? i.e. here we have > pfalse for p0-3, yet we zero z0-7. No, the set of p registers are independent of the z registers. The calling convention states [0] that the predicate registers p0-p3 may be used for parameter passing (if you have an argument which belongs in a p register), so this looks reasonable. [0] https://github.com/ARM-software/abi-aa/blob/8a7b266879c60ca1c76e94ebb279b2dac60ed6a5/aapcs64/aapcs64.rst#scalable-predicate-registers Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124836/new/ https://reviews.llvm.org/D124836 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
