DavidTruby added a comment. > Not sure what you mean by this; LLVM supports extractelement on `<vscale x 16 > x i1>` vectors. I guess the fact that it's a "vscale x 16" element vector > might not be intuitive?
It's a native operation at the LLVM level but not at the ISA level, unlike the data registers. Code quality would be quite poor if we just allowed it naively so I thought it better to disallow it to not give the impression it's easy/free. I will update the text in the commit message to make this more clear. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122732/new/ https://reviews.llvm.org/D122732 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
