MyDeveloperDay added a comment. So out of interest, what is the reason? my assumption is that you wanted to add more for Verilog and you felt adding the extra bools was the wrong design and its better an an enum
bool InCpp11AttributeSpecifier = false; bool InCSharpAttributeSpecifier = false; Does the fact that some aren't exclusive make you think its ok to split it into enums and bools is ok? (no real opinion just wondered what you and others think?) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121907/new/ https://reviews.llvm.org/D121907 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
