zahiraam added inline comments.
================
Comment at: clang/test/CodeGen/X86/avx512fp16-complex.c:123
// X86-NOT: fdiv
- // X86: call {{.*}} @__divhc3(
+ // X86: call {{.*}} @__divsc3(
// X86: ret
----------------
zahiraam wrote:
> pengfei wrote:
> > andrew.w.kaylor wrote:
> > > Why did this change happen?
> > This shouldn't be affect either.
> Still working on this.
Still not sure what the reason but I think it is because of the coerce.
The IR generated for div_half_rc is :
%retval = alloca { half, half }, align 2
%b = alloca { half, half }, align 2
%a.addr = alloca half, align 2
**%coerce = alloca { float, float }, align 4**
%0 = bitcast { half, half }* %b to <2 x half>*
....
I would have expected to have %coerce = alloca { half, half }, align 2
Still not sure what the issue is.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D113107/new/
https://reviews.llvm.org/D113107
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
