eopXD updated this revision to Diff 383987.
eopXD added a comment.
Rebase.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D112987/new/
https://reviews.llvm.org/D112987
Files:
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,8 +33,8 @@
.attribute arch, "rv32ima2p0_fdc"
# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
.attribute arch, "rv32izba1p0"
# CHECK: attribute 5, "rv32i2p0_zba1p0"
@@ -69,56 +69,56 @@
.attribute arch, "rv32ifzfh0p1"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1"
-.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvamo1p0_zvlsseg1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl8192b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl16384b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl16384b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl32768b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32768b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0_zvlsseg1p0"
-.attribute arch, "rv32iv0p10zvl65536b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl65536b1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0_zvlsseg1p0"
-.attribute arch, "rv32i_zve32x0p10"
-# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10_zvlsseg0p10"
+.attribute arch, "rv32i_zve32x1p0"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvl32b1p0_zvlsseg1p0"
-.attribute arch, "rv32i_zve32f0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10_zvlsseg0p10"
+.attribute arch, "rv32i_zve32f1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0_zvlsseg1p0"
-.attribute arch, "rv32i_zve64x0p10"
-# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32i_zve64x1p0"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32i_zve64f0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32i_zve64f1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
-.attribute arch, "rv32i_zve64d0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32i_zve64d1p0"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -42,7 +42,7 @@
; RV32F: .attribute 5, "rv32i2p0_f2p0"
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
@@ -54,7 +54,7 @@
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh0p1_zbb1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -72,8 +72,8 @@
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh0p1_zbb1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
define i32 @addi(i32 %a) {
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -50,7 +50,7 @@
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
- {"v", RISCVExtensionVersion{0, 10}},
+ {"v", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
{"zbb", RISCVExtensionVersion{1, 0}},
{"zbc", RISCVExtensionVersion{1, 0}},
@@ -62,26 +62,26 @@
{"zbs", RISCVExtensionVersion{1, 0}},
{"zbt", RISCVExtensionVersion{0, 93}},
- {"zvamo", RISCVExtensionVersion{0, 10}},
- {"zvlsseg", RISCVExtensionVersion{0, 10}},
- {"zvl32b", RISCVExtensionVersion{0, 10}},
- {"zvl64b", RISCVExtensionVersion{0, 10}},
- {"zvl128b", RISCVExtensionVersion{0, 10}},
- {"zvl256b", RISCVExtensionVersion{0, 10}},
- {"zvl512b", RISCVExtensionVersion{0, 10}},
- {"zvl1024b", RISCVExtensionVersion{0, 10}},
- {"zvl2048b", RISCVExtensionVersion{0, 10}},
- {"zvl4096b", RISCVExtensionVersion{0, 10}},
- {"zvl8192b", RISCVExtensionVersion{0, 10}},
- {"zvl16384b", RISCVExtensionVersion{0, 10}},
- {"zvl32768b", RISCVExtensionVersion{0, 10}},
- {"zvl65536b", RISCVExtensionVersion{0, 10}},
-
- {"zve32x", RISCVExtensionVersion{0, 10}},
- {"zve32f", RISCVExtensionVersion{0, 10}},
- {"zve64x", RISCVExtensionVersion{0, 10}},
- {"zve64f", RISCVExtensionVersion{0, 10}},
- {"zve64d", RISCVExtensionVersion{0, 10}},
+ {"zvamo", RISCVExtensionVersion{1, 0}},
+ {"zvlsseg", RISCVExtensionVersion{1, 0}},
+ {"zvl32b", RISCVExtensionVersion{1, 0}},
+ {"zvl64b", RISCVExtensionVersion{1, 0}},
+ {"zvl128b", RISCVExtensionVersion{1, 0}},
+ {"zvl256b", RISCVExtensionVersion{1, 0}},
+ {"zvl512b", RISCVExtensionVersion{1, 0}},
+ {"zvl1024b", RISCVExtensionVersion{1, 0}},
+ {"zvl2048b", RISCVExtensionVersion{1, 0}},
+ {"zvl4096b", RISCVExtensionVersion{1, 0}},
+ {"zvl8192b", RISCVExtensionVersion{1, 0}},
+ {"zvl16384b", RISCVExtensionVersion{1, 0}},
+ {"zvl32768b", RISCVExtensionVersion{1, 0}},
+ {"zvl65536b", RISCVExtensionVersion{1, 0}},
+
+ {"zve32x", RISCVExtensionVersion{1, 0}},
+ {"zve32f", RISCVExtensionVersion{1, 0}},
+ {"zve64x", RISCVExtensionVersion{1, 0}},
+ {"zve64f", RISCVExtensionVersion{1, 0}},
+ {"zve64d", RISCVExtensionVersion{1, 0}},
{"zfh", RISCVExtensionVersion{0, 1}},
};
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -190,10 +190,10 @@
// CHECK-ZBT-EXT: __riscv_zbt 93000
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32ifdv0p10 -x c -E -dM %s \
+// RUN: -march=rv32ifdv1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ifdv0p10 -x c -E -dM %s \
+// RUN: -march=rv64ifdv1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
// CHECK-V-EXT: __riscv_v 10000
// CHECK-V-EXT: __riscv_vector 1
@@ -208,14 +208,14 @@
// CHECK-ZFH-EXT: __riscv_zfh 1000
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ifdv0p10 -x c -E -dM %s -o - \
+// RUN: -march=rv64ifdv1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s
// CHECK-V-MINVLEN: __riscv_v_max_eew 64
// CHECK-V-MINVLEN: __riscv_v_max_eew_fp 64
// CHECK-V-MINVLEN: __riscv_v_min_vlen 128
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ifdzve64d0p10 -x c -E -dM %s -o - \
+// RUN: -march=rv64ifdzve64d1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s
// CHECK-ZVE64D-EXT: __riscv_v_max_eew 64
// CHECK-ZVE64D-EXT: __riscv_v_max_eew_fp 64
@@ -227,7 +227,7 @@
// CHECK-ZVE64D-EXT: __riscv_zve64x 10000
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ifzve64f0p10 -x c -E -dM %s -o - \
+// RUN: -march=rv64ifzve64f1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s
// CHECK-ZVE64F-EXT: __riscv_v_max_eew 64
// CHECK-ZVE64F-EXT: __riscv_v_max_eew_fp 32
@@ -238,7 +238,7 @@
// CHECK-ZVE64F-EXT: __riscv_zve64x 10000
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izve64x0p10 -x c -E -dM %s -o - \
+// RUN: -march=rv64izve64x1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s
// CHECK-ZVE64X-EXT: __riscv_v_max_eew 64
// CHECK-ZVE64X-EXT: __riscv_v_max_eew_fp 0
@@ -247,7 +247,7 @@
// CHECK-ZVE64X-EXT: __riscv_zve64x 10000
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ifzve32f0p10 -x c -E -dM %s -o - \
+// RUN: -march=rv64ifzve32f1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s
// CHECK-ZVE32F-EXT: __riscv_v_max_eew 32
// CHECK-ZVE32F-EXT: __riscv_v_max_eew_fp 32
@@ -256,7 +256,7 @@
// CHECK-ZVE32F-EXT: __riscv_zve32x 10000
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izve32x0p10 -x c -E -dM %s -o - \
+// RUN: -march=rv64izve32x1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s
// CHECK-ZVE32X-EXT: __riscv_v_max_eew 32
// CHECK-ZVE32X-EXT: __riscv_v_max_eew_fp 0
Index: clang/test/Driver/riscv-arch.c
===================================================================
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -413,7 +413,7 @@
// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension 'v'
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ifdv0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifdv1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
@@ -426,9 +426,9 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvamo -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvamo -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
-// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izve32x0p10_zvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izve32x1p0_zvamo'
// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -menable-experimental-extensions -### %s -c 2>&1 | \
@@ -436,18 +436,18 @@
// RV32-EXPERIMENTAL-ZVAMO-NOVERS: error: invalid arch name 'rv32izvamo'
// RV32-EXPERIMENTAL-ZVAMO-NOVERS: experimental extension requires explicit version number
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvamo0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvamo0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
-// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izve32x0p10_zvamo0p1'
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izve32x1p0_zvamo0p1'
// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for experimental extension 'zvamo'
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvamo0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvamo1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvlsseg -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvlsseg -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
-// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izve32x0p10_zvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izve32x1p0_zvlsseg'
// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions'
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \
@@ -455,25 +455,25 @@
// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg'
// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit version number
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
-// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izve32x0p10_zvlsseg0p1'
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izve32x1p0_zvlsseg0p1'
// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg'
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvlsseg1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvl32b -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvl32b -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
-// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izve32x0p10_zvl32b'
+// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izve32x1p0_zvl32b'
// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s
-// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izve32x0p10_zvl32b0p1'
+// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izve32x1p0_zvl32b0p1'
// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x1p0_zvl32b1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s
// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"
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