Author: Pavel Kosov Date: 2021-10-21T02:39:10+03:00 New Revision: cb9a0dc293cf4ca451d625c6a54e491d8c11e591
URL: https://github.com/llvm/llvm-project/commit/cb9a0dc293cf4ca451d625c6a54e491d8c11e591 DIFF: https://github.com/llvm/llvm-project/commit/cb9a0dc293cf4ca451d625c6a54e491d8c11e591.diff LOG: [ARM] Fix inline assembly referencing floating point registers on soft-float targets Fixes PR: https://bugs.llvm.org/show_bug.cgi?id=52230 Reviewed By: nickdesaulniers Differential Revision: https://reviews.llvm.org/D112135 OS Laboratory, Huawei Russian Research Institute, Saint-Petersburg Added: clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c Modified: clang/lib/Basic/Targets/ARM.cpp clang/lib/Basic/Targets/ARM.h Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 909187df9c04f..fc6b01c87fd22 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -446,6 +446,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasFloat16 = true; ARMCDECoprocMask = 0; HasBFloat16 = false; + FPRegsDisabled = false; // This does not diagnose illegal cases like having both // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64". @@ -522,6 +523,8 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, ARMCDECoprocMask |= (1U << Coproc); } else if (Feature == "+bf16") { HasBFloat16 = true; + } else if (Feature == "-fpregs") { + FPRegsDisabled = true; } } @@ -978,6 +981,8 @@ bool ARMTargetInfo::validateAsmConstraint( case 't': // s0-s31, d0-d31, or q0-q15 case 'w': // s0-s15, d0-d7, or q0-q3 case 'x': // s0-s31, d0-d15, or q0-q7 + if (FPRegsDisabled) + return false; Info.setAllowsRegister(); return true; case 'j': // An immediate integer between 0 and 65535 (valid for MOVW) diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h index 0910064a033b6..d54a049042d60 100644 --- a/clang/lib/Basic/Targets/ARM.h +++ b/clang/lib/Basic/Targets/ARM.h @@ -78,6 +78,7 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo { unsigned Unaligned : 1; unsigned DotProd : 1; unsigned HasMatMul : 1; + unsigned FPRegsDisabled : 1; enum { LDREX_B = (1 << 0), /// byte (8-bit) diff --git a/clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c b/clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c new file mode 100644 index 0000000000000..061e0eeed34e1 --- /dev/null +++ b/clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c @@ -0,0 +1,29 @@ +// REQUIRES: arm-registered-target +// RUN: %clang_cc1 -triple arm -target-feature -fpregs -verify=arm-nofp %s + +// w: A 32, 64, or 128-bit floating-point/SIMD register: s0-s31, d0-d31, or q0-q15. +float test_w(float x) { + __asm__("vsqrt.f32 %0, %1" + : "=w"(x) + : "w"(x)); // No error expected. + // arm-nofp-error@7 {{invalid output constraint '=w' in asm}} + return x; +} + +// x: A 32, 64, or 128-bit floating-point/SIMD register: s0-s15, d0-d7, or q0-q3. +float test_x(float x) { + __asm__("vsqrt.f32 %0, %1" + : "=x"(x) + : "x"(x)); // No error expected. + // arm-nofp-error@16 {{invalid output constraint '=x' in asm}} + return x; +} + +// t: A 32, 64, or 128-bit floating-point/SIMD register: s0-s31, d0-d15, or q0-q7. +float test_t(float x) { + __asm__("vsqrt.f32 %0, %1" + : "=t"(x) + : "t"(x)); // No error expected. + // arm-nofp-error@25 {{invalid output constraint '=t' in asm}} + return x; +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
