mubashar_ updated this revision to Diff 372698.
mubashar_ added a comment.
Updated release notes to solve a merge conflict.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109825/new/
https://reviews.llvm.org/D109825
Files:
clang/docs/ReleaseNotes.rst
clang/test/Driver/aarch64-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/unittests/Support/TargetParserTest.cpp
Index: llvm/unittests/Support/TargetParserTest.cpp
===================================================================
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -983,6 +983,14 @@
AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
AArch64::AEK_SSBS,
"8.2-A"),
+ ARMCPUTestParams("cortex-a510", "armv8.3-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_RDM | AArch64::AEK_RCPC |
+ AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_DOTPROD | AArch64::AEK_MTE,
+ "8.3-A"),
ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1164,7 +1172,7 @@
AArch64::AEK_LSE | AArch64::AEK_RDM,
"8.2-A")));
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -59,6 +59,7 @@
CortexA77,
CortexA78,
CortexA78C,
+ CortexA510,
CortexR82,
CortexX1,
ExynosM3,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -193,6 +193,9 @@
// FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128;
break;
+ case CortexA510:
+ PrefFunctionLogAlignment = 4;
+ break;
}
}
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -1048,6 +1048,26 @@
FeatureSSBS,
FeatureSVE]>;
+def ProcCortexA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+ "CortexA510", "Cortex-A510 ARM processors", [
+ HasV8_3aOps,
+ FeatureCrypto,
+ FeatureFPARMv8,
+ FeatureFuseAES,
+ FeatureNEON,
+ FeaturePerfMon,
+ FeaturePostRAScheduler,
+ FeatureSPE,
+ FeatureAM,
+ FeatureMPAM,
+ FeatureETE,
+ FeatureMTE,
+ FeatureSVE2,
+ FeatureSVE2BitPerm,
+ FeatureFullFP16,
+ FeatureFP16FML,
+ FeatureDotProd]>;
+
def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [
FeatureCrypto,
@@ -1187,6 +1207,7 @@
def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
+def : ProcessorModel<"cortex-a510", CortexA57Model, [ProcCortexA510]>;
def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===================================================================
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -176,6 +176,10 @@
(AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
AArch64::AEK_RCPC | AArch64::AEK_FP16 | AArch64::AEK_BF16 |
AArch64::AEK_DOTPROD ))
+AARCH64_CPU_NAME("cortex-a510", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_MTE | AArch64::AEK_SVE2 |
+ AArch64::AEK_SVE2BITPERM | AArch64::AEK_DOTPROD |
+ AArch64::AEK_RAS))
AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_NONE))
AARCH64_CPU_NAME("apple-a7", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
Index: clang/test/Driver/aarch64-cpus.c
===================================================================
--- clang/test/Driver/aarch64-cpus.c
+++ clang/test/Driver/aarch64-cpus.c
@@ -788,6 +788,9 @@
// RUN: %clang -target aarch64 -march=armv8-a+ras -### -c %s 2>&1 | FileCheck -check-prefix=V8ARAS -check-prefix=GENERIC %s
// V8ARAS: "-target-feature" "+ras"
+// RUN: %clang -target aarch64 -mcpu=cortex-a510 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A510 %s
+// CORTEX-A510: "-cc1" {{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a510"
+
// ================== Check whether -march accepts mixed-case values.
// RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
// RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
Index: clang/docs/ReleaseNotes.rst
===================================================================
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -83,6 +83,9 @@
- RISC-V SiFive S54 (``sifive-s54``).
- RISC-V SiFive S76 (``sifive-s76``).
+- Support has been added for the following processors (command-line identifiers in parentheses):
+ - Arm Cortex-A510 (cortex-a510).
+
Removed Compiler Flags
-------------------------
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