RKSimon added a comment. > Regarding this case, we already have a different name with GCC, I think it > worthwhile to use a different order for the swapping optimization. > With a bit research on AVX512IFMA, I found: > > 1. The use of C, A, B order in GCC is not consistent on its AVX512IFMA > builtins. It supposes GCC should change to A, B, C order if considering > consistency; > 2. We aren't consistent on AVX512IFMA builtins with GCC either due to the use > of select.
Do we have any builtins with the same name as gcc but different operands/behaviours? Those are the only ones that I'd be worried about. > By the way, GCC folks told me GCC has ability to specify arbitrary operands > that can be commutative. But I found both SDNode and MI only have ability on > the first 2 operands, which is insufficient for instruction like CFMA. Do you > know if we have other mechanism for commutable operands? Doesn't X86InstrInfo::findCommutedOpIndices handle these cases? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109658/new/ https://reviews.llvm.org/D109658 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
