kstoimenov added inline comments.
================ Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1426 + OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8) + .addReg(X86::ECX) + .addReg(X86::ECX) ---------------- vitalybuka wrote: > kstoimenov wrote: > > vitalybuka wrote: > > > what is in ECX register here? > > Should be NoRegister. Done. > Why NoRegister update is not reflected in tests? The instruction template for AND32ri8 expects 2 registers for some reason, which I am not sure why. If I provide only one register I get a clang crash. The emitted instruction is what I want so I didn't dig much deeper into it. ================ Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll:94 +; CHECK-NEXT: movq [[REG]], %rcx +; CHECK-NEXT: andl $7, %ecx +; CHECK-NEXT: addl $1, %ecx ---------------- vitalybuka wrote: > What is ECX here? ECX is the lower 3 bits of the address. Is is the second part of the check "((Addr & 7) + AccessSize > k)". Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
