Conanap created this revision.
Conanap added reviewers: nemanjai, saghir, PowerPC.
Conanap added projects: LLVM, PowerPC, clang.
Herald added a subscriber: kbarton.
Conanap requested review of this revision.
The following example generates code that can be completed in two instructions
instead:
void testutof(vector unsigned short a, float *ptr) {
*ptr = a[0];
}
The patch improves this code gen.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D100604
Files:
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
Index: llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
@@ -34,18 +34,12 @@
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3
-; CHECK-P9-NEXT: li r3, 0
-; CHECK-P9-NEXT: vextubrx r3, r3, v2
-; CHECK-P9-NEXT: clrlwi r3, r3, 24
-; CHECK-P9-NEXT: mtfprwz f0, r3
-; CHECK-P9-NEXT: li r3, 1
-; CHECK-P9-NEXT: xscvuxdsp f0, f0
-; CHECK-P9-NEXT: vextubrx r3, r3, v2
-; CHECK-P9-NEXT: clrlwi r3, r3, 24
+; CHECK-P9-NEXT: vextractub v3, v2, 15
+; CHECK-P9-NEXT: vextractub v2, v2, 14
+; CHECK-P9-NEXT: xscvuxdsp f0, v3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT: mtfprwz f0, r3
-; CHECK-P9-NEXT: xscvuxdsp f0, f0
+; CHECK-P9-NEXT: xscvuxdsp f0, v2
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3
@@ -55,17 +49,11 @@
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3
-; CHECK-BE-NEXT: li r3, 1
-; CHECK-BE-NEXT: vextublx r3, r3, v2
-; CHECK-BE-NEXT: clrlwi r3, r3, 24
-; CHECK-BE-NEXT: mtfprwz f0, r3
-; CHECK-BE-NEXT: li r3, 0
-; CHECK-BE-NEXT: xscvuxdsp f0, f0
-; CHECK-BE-NEXT: vextublx r3, r3, v2
-; CHECK-BE-NEXT: clrlwi r3, r3, 24
+; CHECK-BE-NEXT: vextractub v3, v2, 2
+; CHECK-BE-NEXT: vextractub v2, v2, 0
+; CHECK-BE-NEXT: xscvuxdsp f0, v3
; CHECK-BE-NEXT: xscvdpspn v3, f0
-; CHECK-BE-NEXT: mtfprwz f0, r3
-; CHECK-BE-NEXT: xscvuxdsp f0, f0
+; CHECK-BE-NEXT: xscvuxdsp f0, v2
; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2
@@ -299,18 +287,14 @@
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3
-; CHECK-P9-NEXT: li r3, 0
-; CHECK-P9-NEXT: vextubrx r3, r3, v2
-; CHECK-P9-NEXT: extsb r3, r3
-; CHECK-P9-NEXT: mtfprwa f0, r3
-; CHECK-P9-NEXT: li r3, 1
-; CHECK-P9-NEXT: xscvsxdsp f0, f0
-; CHECK-P9-NEXT: vextubrx r3, r3, v2
-; CHECK-P9-NEXT: extsb r3, r3
+; CHECK-P9-NEXT: vextractub v3, v2, 15
+; CHECK-P9-NEXT: vextractub v2, v2, 14
+; CHECK-P9-NEXT: vextsh2d v3, v3
+; CHECK-P9-NEXT: vextsh2d v2, v2
+; CHECK-P9-NEXT: xscvsxdsp f0, v3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT: mtfprwa f0, r3
-; CHECK-P9-NEXT: xscvsxdsp f0, f0
+; CHECK-P9-NEXT: xscvsxdsp f0, v2
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3
@@ -320,17 +304,13 @@
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3
-; CHECK-BE-NEXT: li r3, 1
-; CHECK-BE-NEXT: vextublx r3, r3, v2
-; CHECK-BE-NEXT: extsb r3, r3
-; CHECK-BE-NEXT: mtfprwa f0, r3
-; CHECK-BE-NEXT: li r3, 0
-; CHECK-BE-NEXT: xscvsxdsp f0, f0
-; CHECK-BE-NEXT: vextublx r3, r3, v2
-; CHECK-BE-NEXT: extsb r3, r3
+; CHECK-BE-NEXT: vextractub v3, v2, 2
+; CHECK-BE-NEXT: vextractub v2, v2, 0
+; CHECK-BE-NEXT: vextsh2d v3, v3
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsxdsp f0, v3
; CHECK-BE-NEXT: xscvdpspn v3, f0
-; CHECK-BE-NEXT: mtfprwa f0, r3
-; CHECK-BE-NEXT: xscvsxdsp f0, f0
+; CHECK-BE-NEXT: xscvsxdsp f0, v2
; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2
Index: llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
@@ -34,18 +34,12 @@
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3
-; CHECK-P9-NEXT: li r3, 0
-; CHECK-P9-NEXT: vextuhrx r3, r3, v2
-; CHECK-P9-NEXT: clrlwi r3, r3, 16
-; CHECK-P9-NEXT: mtfprwz f0, r3
-; CHECK-P9-NEXT: li r3, 2
-; CHECK-P9-NEXT: xscvuxdsp f0, f0
-; CHECK-P9-NEXT: vextuhrx r3, r3, v2
-; CHECK-P9-NEXT: clrlwi r3, r3, 16
+; CHECK-P9-NEXT: vextractuh v3, v2, 14
+; CHECK-P9-NEXT: vextractuh v2, v2, 12
+; CHECK-P9-NEXT: xscvuxdsp f0, v3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT: mtfprwz f0, r3
-; CHECK-P9-NEXT: xscvuxdsp f0, f0
+; CHECK-P9-NEXT: xscvuxdsp f0, v2
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3
@@ -55,17 +49,11 @@
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3
-; CHECK-BE-NEXT: li r3, 2
-; CHECK-BE-NEXT: vextuhlx r3, r3, v2
-; CHECK-BE-NEXT: clrlwi r3, r3, 16
-; CHECK-BE-NEXT: mtfprwz f0, r3
-; CHECK-BE-NEXT: li r3, 0
-; CHECK-BE-NEXT: xscvuxdsp f0, f0
-; CHECK-BE-NEXT: vextuhlx r3, r3, v2
-; CHECK-BE-NEXT: clrlwi r3, r3, 16
+; CHECK-BE-NEXT: vextractuh v3, v2, 2
+; CHECK-BE-NEXT: vextractuh v2, v2, 0
+; CHECK-BE-NEXT: xscvuxdsp f0, v3
; CHECK-BE-NEXT: xscvdpspn v3, f0
-; CHECK-BE-NEXT: mtfprwz f0, r3
-; CHECK-BE-NEXT: xscvuxdsp f0, f0
+; CHECK-BE-NEXT: xscvuxdsp f0, v2
; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2
@@ -266,18 +254,14 @@
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3
-; CHECK-P9-NEXT: li r3, 0
-; CHECK-P9-NEXT: vextuhrx r3, r3, v2
-; CHECK-P9-NEXT: extsh r3, r3
-; CHECK-P9-NEXT: mtfprwa f0, r3
-; CHECK-P9-NEXT: li r3, 2
-; CHECK-P9-NEXT: xscvsxdsp f0, f0
-; CHECK-P9-NEXT: vextuhrx r3, r3, v2
-; CHECK-P9-NEXT: extsh r3, r3
+; CHECK-P9-NEXT: vextractuh v3, v2, 14
+; CHECK-P9-NEXT: vextractuh v2, v2, 12
+; CHECK-P9-NEXT: vextsh2d v3, v3
+; CHECK-P9-NEXT: vextsh2d v2, v2
+; CHECK-P9-NEXT: xscvsxdsp f0, v3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT: mtfprwa f0, r3
-; CHECK-P9-NEXT: xscvsxdsp f0, f0
+; CHECK-P9-NEXT: xscvsxdsp f0, v2
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3
@@ -287,17 +271,13 @@
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3
-; CHECK-BE-NEXT: li r3, 2
-; CHECK-BE-NEXT: vextuhlx r3, r3, v2
-; CHECK-BE-NEXT: extsh r3, r3
-; CHECK-BE-NEXT: mtfprwa f0, r3
-; CHECK-BE-NEXT: li r3, 0
-; CHECK-BE-NEXT: xscvsxdsp f0, f0
-; CHECK-BE-NEXT: vextuhlx r3, r3, v2
-; CHECK-BE-NEXT: extsh r3, r3
+; CHECK-BE-NEXT: vextractuh v3, v2, 2
+; CHECK-BE-NEXT: vextractuh v2, v2, 0
+; CHECK-BE-NEXT: vextsh2d v3, v3
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsxdsp f0, v3
; CHECK-BE-NEXT: xscvdpspn v3, f0
-; CHECK-BE-NEXT: mtfprwa f0, r3
-; CHECK-BE-NEXT: xscvsxdsp f0, f0
+; CHECK-BE-NEXT: xscvsxdsp f0, v2
; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2
Index: llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
+++ llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
@@ -14,31 +14,19 @@
define dso_local <2 x double> @test1(<8 x i16> %a) {
; P9BE-LABEL: test1:
; P9BE: # %bb.0: # %entry
-; P9BE-NEXT: li r3, 0
-; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: clrlwi r3, r3, 16
-; P9BE-NEXT: mtfprwz f0, r3
-; P9BE-NEXT: li r3, 2
-; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: xscvuxddp f0, f0
-; P9BE-NEXT: clrlwi r3, r3, 16
-; P9BE-NEXT: mtfprwz f1, r3
-; P9BE-NEXT: xscvuxddp f1, f1
+; P9BE-NEXT: vextractuh v3, v2, 0
+; P9BE-NEXT: vextractuh v2, v2, 2
+; P9BE-NEXT: xscvuxddp f0, v3
+; P9BE-NEXT: xscvuxddp f1, v2
; P9BE-NEXT: xxmrghd v2, vs0, vs1
; P9BE-NEXT: blr
;
; P9LE-LABEL: test1:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: li r3, 0
-; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: clrlwi r3, r3, 16
-; P9LE-NEXT: mtfprwz f0, r3
-; P9LE-NEXT: li r3, 2
-; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: xscvuxddp f0, f0
-; P9LE-NEXT: clrlwi r3, r3, 16
-; P9LE-NEXT: mtfprwz f1, r3
-; P9LE-NEXT: xscvuxddp f1, f1
+; P9LE-NEXT: vextractuh v3, v2, 14
+; P9LE-NEXT: vextractuh v2, v2, 12
+; P9LE-NEXT: xscvuxddp f0, v3
+; P9LE-NEXT: xscvuxddp f1, v2
; P9LE-NEXT: xxmrghd v2, vs1, vs0
; P9LE-NEXT: blr
;
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -4126,7 +4126,7 @@
(f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;
}
-// (Un)Signed HWord vector extract -> QP
+// (Un)Signed HWord vector extract -> QP/DP/SP
foreach Idx = 0-7 in {
def : Pat<(f128 (sint_to_fp
(i32 (sext_inreg
@@ -4139,6 +4139,32 @@
(and (i32 (vector_extract v8i16:$src, Idx)), 65535))),
(f128 (XSCVUDQP (EXTRACT_SUBREG
(VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
+ def : Pat<(f32 (PPCfcfidus
+ (f64 (PPCmtvsrz
+ (and (i32 (vector_extract v8i16:$src, Idx)), 65535)
+ )))),
+ (f32 (XSCVUXDSP (EXTRACT_SUBREG
+ (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
+ def : Pat<(f32 (PPCfcfids
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg (vector_extract v8i16:$src, Idx), i16))
+ )))),
+ (f32 (XSCVSXDSP (EXTRACT_SUBREG
+ (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
+ sub_64)))>;
+ def : Pat<(f64 (PPCfcfidu
+ (f64 (PPCmtvsrz
+ (and (i32 (vector_extract v8i16:$src, Idx)), 65535)
+ )))),
+ (f64 (XSCVUXDDP (EXTRACT_SUBREG
+ (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
+ def : Pat<(f64 (PPCfcfid
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg (vector_extract v8i16:$src, Idx), i16))
+ )))),
+ (f64 (XSCVSXDDP (EXTRACT_SUBREG
+ (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
+ sub_64)))>;
}
// (Un)Signed Byte vector extract -> QP
@@ -4152,6 +4178,33 @@
(and (i32 (vector_extract v16i8:$src, Idx)), 255))),
(f128 (XSCVUDQP
(EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>;
+
+ def : Pat<(f32 (PPCfcfidus
+ (f64 (PPCmtvsrz
+ (and (i32 (vector_extract v16i8:$src, Idx)), 255)
+ )))),
+ (f32 (XSCVUXDSP (EXTRACT_SUBREG
+ (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
+ def : Pat<(f32 (PPCfcfids
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg (vector_extract v16i8:$src, Idx), i8))
+ )))),
+ (f32 (XSCVSXDSP (EXTRACT_SUBREG
+ (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
+ sub_64)))>;
+ def : Pat<(f64 (PPCfcfidu
+ (f64 (PPCmtvsrz
+ (and (i32 (vector_extract v16i8:$src, Idx)), 255)
+ )))),
+ (f64 (XSCVUXDDP (EXTRACT_SUBREG
+ (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
+ def : Pat<(f64 (PPCfcfid
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg (vector_extract v16i8:$src, Idx), i8))
+ )))),
+ (f64 (XSCVSXDDP (EXTRACT_SUBREG
+ (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
+ sub_64)))>;
}
// Unsiged int in vsx register -> QP
@@ -4322,7 +4375,7 @@
(f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;
}
-// (Un)Signed HWord vector extract -> QP
+// (Un)Signed HWord vector extract -> QP/DP/SP
// The Nested foreach lists identifies the vector element and corresponding
// register byte location.
foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in {
@@ -4338,9 +4391,40 @@
65535))),
(f128 (XSCVUDQP (EXTRACT_SUBREG
(VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
+ def : Pat<(f32 (PPCfcfidus
+ (f64 (PPCmtvsrz
+ (and (i32
+ (vector_extract v8i16:$src, !head(Idx))), 65535)
+ )))),
+ (f32 (XSCVUXDSP (EXTRACT_SUBREG
+ (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
+ def : Pat<(f32 (PPCfcfids
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg
+ (vector_extract v8i16:$src, !head(Idx)), i16))
+ )))),
+ (f32 (XSCVSXDSP
+ (EXTRACT_SUBREG (VEXTSH2D
+ (VEXTRACTUH !head(!tail(Idx)), $src)),
+ sub_64)))>;
+ def : Pat<(f64 (PPCfcfidu
+ (f64 (PPCmtvsrz
+ (and (i32
+ (vector_extract v8i16:$src, !head(Idx))), 65535)
+ )))),
+ (f64 (XSCVUXDDP (EXTRACT_SUBREG
+ (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
+ def : Pat<(f64 (PPCfcfid
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg
+ (vector_extract v8i16:$src, !head(Idx)), i16)))))),
+ (f64 (XSCVSXDDP
+ (EXTRACT_SUBREG (VEXTSH2D
+ (VEXTRACTUH !head(!tail(Idx)), $src)),
+ sub_64)))>;
}
-// (Un)Signed Byte vector extract -> QP
+// (Un)Signed Byte vector extract -> QP/DP/SP
foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7],
[9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in {
def : Pat<(f128 (sint_to_fp
@@ -4356,6 +4440,47 @@
(f128 (XSCVUDQP
(EXTRACT_SUBREG
(VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
+
+ def : Pat<(f32 (PPCfcfidus
+ (f64 (PPCmtvsrz
+ (and (i32
+ (vector_extract v16i8:$src, !head(Idx))), 255)
+ )))),
+ (f32 (XSCVUXDSP (EXTRACT_SUBREG
+ (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
+ def : Pat<(f32 (PPCfcfids
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg
+ (vector_extract v16i8:$src, !head(Idx)), i8))
+ )))),
+ (f32 (XSCVSXDSP
+ (EXTRACT_SUBREG (VEXTSH2D
+ (VEXTRACTUB !head(!tail(Idx)), $src)),
+ sub_64)))>;
+ def : Pat<(f64 (PPCfcfidu
+ (f64 (PPCmtvsrz
+ (and (i32
+ (vector_extract v16i8:$src, !head(Idx))), 255)
+ )))),
+ (f64 (XSCVUXDDP (EXTRACT_SUBREG
+ (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
+ def : Pat<(f64 (PPCfcfidu
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg
+ (vector_extract v16i8:$src, !head(Idx)), i8)))))),
+ (f64 (XSCVSXDDP
+ (EXTRACT_SUBREG (VEXTSH2D
+ (VEXTRACTUB !head(!tail(Idx)), $src)),
+ sub_64)))>;
+
+ def : Pat<(f64 (PPCfcfid
+ (f64 (PPCmtvsra
+ (i32 (sext_inreg
+ (vector_extract v16i8:$src, !head(Idx)), i8)))))),
+ (f64 (XSCVSXDDP
+ (EXTRACT_SUBREG (VEXTSH2D
+ (VEXTRACTUH !head(!tail(Idx)), $src)),
+ sub_64)))>;
}
// Unsiged int in vsx register -> QP
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