Author: Craig Topper Date: 2021-04-02T23:49:44-07:00 New Revision: b4f2e8060075761dd0e9727ea01ca0142b4e767f
URL: https://github.com/llvm/llvm-project/commit/b4f2e8060075761dd0e9727ea01ca0142b4e767f DIFF: https://github.com/llvm/llvm-project/commit/b4f2e8060075761dd0e9727ea01ca0142b4e767f.diff LOG: [RISCV] Refactor conversion of B extensions to IR intrinsics a little to reduce clang binary size. These all pass 1 type to getIntrinsic. So rather than assigning IntrinsicTypes for each builtin which invokes the SmallVector constructor, just select the intrinsic ID with a switch and share a single assignment of IntrinsicTypes. Added: Modified: clang/lib/CodeGen/CGBuiltin.cpp Removed: ################################################################################ diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 80e48fbceef4..6b43a8de218e 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -17875,64 +17875,71 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, // Required for overloaded intrinsics. llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes; switch (BuiltinID) { -#include "clang/Basic/riscv_vector_builtin_cg.inc" - - // Zbb + default: llvm_unreachable("unexpected builtin ID"); case RISCV::BI__builtin_riscv_orc_b_32: case RISCV::BI__builtin_riscv_orc_b_64: - ID = Intrinsic::riscv_orc_b; - IntrinsicTypes = {ResultType}; - break; - - // Zbc case RISCV::BI__builtin_riscv_clmul: - ID = Intrinsic::riscv_clmul; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_clmulh: - ID = Intrinsic::riscv_clmulh; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_clmulr: - ID = Intrinsic::riscv_clmulr; - IntrinsicTypes = {ResultType}; - break; - - // Zbr case RISCV::BI__builtin_riscv_crc32_b: - ID = Intrinsic::riscv_crc32_b; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_crc32_h: - ID = Intrinsic::riscv_crc32_h; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_crc32_w: - ID = Intrinsic::riscv_crc32_w; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_crc32_d: - ID = Intrinsic::riscv_crc32_d; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_crc32c_b: - ID = Intrinsic::riscv_crc32c_b; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_crc32c_h: - ID = Intrinsic::riscv_crc32c_h; - IntrinsicTypes = {ResultType}; - break; case RISCV::BI__builtin_riscv_crc32c_w: - ID = Intrinsic::riscv_crc32c_w; - IntrinsicTypes = {ResultType}; - break; - case RISCV::BI__builtin_riscv_crc32c_d: - ID = Intrinsic::riscv_crc32c_d; + case RISCV::BI__builtin_riscv_crc32c_d: { + switch (BuiltinID) { + default: llvm_unreachable("unexpected builtin ID"); + // Zbb + case RISCV::BI__builtin_riscv_orc_b_32: + case RISCV::BI__builtin_riscv_orc_b_64: + ID = Intrinsic::riscv_orc_b; + break; + + // Zbc + case RISCV::BI__builtin_riscv_clmul: + ID = Intrinsic::riscv_clmul; + break; + case RISCV::BI__builtin_riscv_clmulh: + ID = Intrinsic::riscv_clmulh; + break; + case RISCV::BI__builtin_riscv_clmulr: + ID = Intrinsic::riscv_clmulr; + break; + + // Zbr + case RISCV::BI__builtin_riscv_crc32_b: + ID = Intrinsic::riscv_crc32_b; + break; + case RISCV::BI__builtin_riscv_crc32_h: + ID = Intrinsic::riscv_crc32_h; + break; + case RISCV::BI__builtin_riscv_crc32_w: + ID = Intrinsic::riscv_crc32_w; + break; + case RISCV::BI__builtin_riscv_crc32_d: + ID = Intrinsic::riscv_crc32_d; + break; + case RISCV::BI__builtin_riscv_crc32c_b: + ID = Intrinsic::riscv_crc32c_b; + break; + case RISCV::BI__builtin_riscv_crc32c_h: + ID = Intrinsic::riscv_crc32c_h; + break; + case RISCV::BI__builtin_riscv_crc32c_w: + ID = Intrinsic::riscv_crc32c_w; + break; + case RISCV::BI__builtin_riscv_crc32c_d: + ID = Intrinsic::riscv_crc32c_d; + break; + } + IntrinsicTypes = {ResultType}; break; - default: - llvm_unreachable("unexpected builtin ID"); + } + // Vector builtins are handled from here. +#include "clang/Basic/riscv_vector_builtin_cg.inc" } assert(ID != Intrinsic::not_intrinsic); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
