This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9b29610228c8: Use unary CreateShuffleVector if possible (authored by aqjune).
Changed prior to commit: https://reviews.llvm.org/D93923?vs=314108&id=314109#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93923/new/ https://reviews.llvm.org/D93923 Files: clang/lib/CodeGen/CGBuiltin.cpp clang/lib/CodeGen/CGExpr.cpp clang/lib/CodeGen/CGExprScalar.cpp clang/test/CodeGen/X86/avx-builtins.c clang/test/CodeGen/X86/avx2-builtins.c clang/test/CodeGen/X86/avx512-reduceMinMaxIntrin.c clang/test/CodeGen/X86/avx512bw-builtins.c clang/test/CodeGen/X86/avx512dq-builtins.c clang/test/CodeGen/X86/avx512f-builtins.c clang/test/CodeGen/X86/avx512vl-builtins-constrained.c clang/test/CodeGen/X86/avx512vl-builtins.c clang/test/CodeGen/X86/avx512vlbw-builtins.c clang/test/CodeGen/X86/avx512vldq-builtins.c clang/test/CodeGen/X86/f16c-builtins-constrained.c clang/test/CodeGen/X86/f16c-builtins.c clang/test/CodeGen/X86/sse2-builtins.c clang/test/CodeGen/arm-mve-intrinsics/vmovl.c clang/test/CodeGen/arm-mve-intrinsics/vmovn.c clang/test/CodeGen/arm-mve-intrinsics/vrev.c clang/test/CodeGen/arm64-abi-vector.c clang/test/CodeGenOpenCL/as_type.cl clang/test/CodeGenOpenCL/partial_initializer.cl clang/test/CodeGenOpenCL/preserve_vec3.cl clang/test/CodeGenOpenCL/vectorLoadStore.cl clang/test/CodeGenOpenCL/vector_literals_valid.cl llvm/lib/Analysis/VectorUtils.cpp llvm/lib/CodeGen/CodeGenPrepare.cpp llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp llvm/lib/IR/AutoUpgrade.cpp llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp llvm/lib/Target/X86/X86InterleavedAccess.cpp llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp llvm/lib/Transforms/Scalar/SROA.cpp llvm/lib/Transforms/Utils/LoopUtils.cpp llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll llvm/test/CodeGen/AMDGPU/lower-kernargs.ll llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll llvm/test/CodeGen/Generic/expand-experimental-reductions.ll llvm/test/Instrumentation/MemorySanitizer/clmul.ll llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll llvm/test/Transforms/InstCombine/canonicalize-vector-insert.ll llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-inseltpoison.ll llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-inseltpoison.ll llvm/test/Transforms/InterleavedAccess/X86/interleavedStore.ll llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll llvm/test/Transforms/LoopVectorize/reduction.ll llvm/test/Transforms/LoopVectorize/select-reduction.ll llvm/test/Transforms/LowerMatrixIntrinsics/bigger-expressions-double.ll llvm/test/Transforms/LowerMatrixIntrinsics/const-gep.ll llvm/test/Transforms/LowerMatrixIntrinsics/load-align-volatile.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-add-sub-double-row-major.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-double-contraction-fmf.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-double-contraction.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-double-row-major.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-double.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-float-contraction-fmf.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-float-contraction.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-float.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-volatile.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-i32-row-major.ll llvm/test/Transforms/LowerMatrixIntrinsics/multiply-i32.ll llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backward.ll llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll llvm/test/Transforms/LowerMatrixIntrinsics/propagate-forward.ll llvm/test/Transforms/LowerMatrixIntrinsics/propagate-mixed-users.ll llvm/test/Transforms/LowerMatrixIntrinsics/store-align-volatile.ll llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-double.ll llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-float.ll llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-i32.ll llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-double.ll llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-float.ll llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-i32.ll llvm/test/Transforms/LowerMatrixIntrinsics/transpose-double-row-major.ll llvm/test/Transforms/LowerMatrixIntrinsics/transpose-double.ll llvm/test/Transforms/LowerMatrixIntrinsics/transpose-float-row-major.ll llvm/test/Transforms/LowerMatrixIntrinsics/transpose-float.ll llvm/test/Transforms/LowerMatrixIntrinsics/transpose-i32-row-major.ll llvm/test/Transforms/LowerMatrixIntrinsics/transpose-i32.ll llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll llvm/test/Transforms/SROA/vector-promotion.ll llvm/unittests/IR/PatternMatch.cpp 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