fpetrogalli created this revision. fpetrogalli added reviewers: peterwaller-arm, paulwalker-arm, efriedma, c-rhodes. Herald added subscribers: cfe-commits, psnobl, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. fpetrogalli requested review of this revision.
The following macros are activated when the compiler is targeting SVE with the option `-msve-vector-bits=<N>`: 1. __ARM_FEATURE_SVE_VECTOR_OPERATORS 2. __ARM_FEATURE_SVE_PREDICATE_OPERATORS The behavior implied by the macros is described in sections 3.7.3.3 and 3.7.3.4 respectively of the SVE ACLE (Version 00bet6) that can be found at https://developer.arm.com/documentation/100987/latest Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D90956 Files: clang/lib/Basic/Targets/AArch64.cpp clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_PREDICATE_OPERATORS.c clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_PREDICATE_OPERATORS.cpp clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS-expected-error-on-address.c clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp clang/test/Preprocessor/aarch64-target-features.c
Index: clang/test/Preprocessor/aarch64-target-features.c =================================================================== --- clang/test/Preprocessor/aarch64-target-features.c +++ clang/test/Preprocessor/aarch64-target-features.c @@ -440,14 +440,11 @@ // CHECK-BFLOAT: __ARM_FEATURE_BF16_VECTOR_ARITHMETIC 1 // ================== Check sve-vector-bits flag. -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=128 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-128 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=256 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-256 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=512 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-512 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=1024 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-1024 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-2048 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-2048 %s -// CHECK-SVE-VECTOR-BITS-128: __ARM_FEATURE_SVE_BITS 128 -// CHECK-SVE-VECTOR-BITS-256: __ARM_FEATURE_SVE_BITS 256 -// CHECK-SVE-VECTOR-BITS-512: __ARM_FEATURE_SVE_BITS 512 -// CHECK-SVE-VECTOR-BITS-1024: __ARM_FEATURE_SVE_BITS 1024 -// CHECK-SVE-VECTOR-BITS-2048: __ARM_FEATURE_SVE_BITS 2048 +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=128 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=128 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=256 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=256 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=512 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=512 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=1024 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=1024 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=2048 %s +// CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_BITS [[#VBITS:]] +// CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_PREDICATE_OPERATORS 1 +// CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_VECTOR_OPERATORS 1 Index: clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp =================================================================== --- /dev/null +++ clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp @@ -0,0 +1,27 @@ +// RUN: %clang -x c++ -S -emit-llvm -c -O1 -o - %s -target aarch64-gnu-linux \ +// RUN: -march=armv8-a+sve -msve-vector-bits=256 | FileCheck %s +// RUN: %clang -x c++ -S -emit-llvm -c -O1 -o - %s -target aarch64-gnu-linux \ +// RUN: -march=armv8-a+sve -msve-vector-bits=512 | FileCheck %s --check-prefix=CHECK512 +// REQUIRES: aarch64-registered-target + +// Examples taken from section 3.7.3.3 of the SVE ACLE (Version +// 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest + +#include <arm_sve.h> + +// Page 27, item 1. +#if __ARM_FEATURE_SVE_BITS == 512 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK512-LABEL: define {{.*}} <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj512EES_(<vscale x 4 x i32> %x.coerce, <vscale x 4 x i32> %y.coerce) +typedef svint32_t vec __attribute__((arm_sve_vector_bits(512))); +auto f(vec x, vec y) { return x + y; } // Returns a vec. +#endif + +// Page 27, item 3. +typedef int8_t vec1 __attribute__((vector_size(32))); +void f(vec1); +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); +// CHECK-LABEL: @_Z1g9__SVE_VLSIu10__SVInt8_tLj256EE( +void g(vec2 x) { f(x); } // OK +#endif Index: clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c =================================================================== --- /dev/null +++ clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c @@ -0,0 +1,38 @@ +// RUN: %clang -S -emit-llvm -c -O1 -o - %s -target aarch64-gnu-linux \ +// RUN: -march=armv8-a+sve -msve-vector-bits=256 | FileCheck %s +// REQUIRES: aarch64-registered-target + +// Examples taken from section 3.7.3.3 of the SVE ACLE (Version +// 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest + +#include <arm_sve.h> + +// Page 27, item 1 +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK-LABEL: @x = dso_local local_unnamed_addr global <4 x i64> <i64 0, i64 1, i64 2, i64 3>, align 16 +typedef svint64_t vec256 __attribute__((arm_sve_vector_bits(256))); +vec256 x = {0, 1, 2, 3}; +#endif + +// Page 27, item 2. We can not change the ABI of existing vector +// types, including vec_int8. That's why in the SVE ACLE, VLST is +// distinct from, but mostly interchangeable with, the corresponding +// GNUT. VLST is treated for ABI purposes like an SVE type but GNUT +// continues to be a normal GNU vector type, with base Armv8-A PCS +// rules. +typedef int8_t vec_int8 __attribute__((vector_size(32))); +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK-LABEL: {{.*}} void @f2(<32 x i8>* noalias nocapture sret(<32 x i8>) align 16 %agg.result, <32 x i8>* nocapture readonly %0) +vec_int8 f2(vec_int8 x) { return svasrd_x(svptrue_b8(), x, 1); } +#endif + +// Page 27, item 3. +typedef int8_t vec1 __attribute__((vector_size(32))); +void f3(vec1); +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); +// CHECK-LABEL: define dso_local void @g(<vscale x 16 x i8> %x.coerce) +// CHECK-LABEL: declare dso_local void @f3(<32 x i8>*) +void g(vec2 x) { f3(x); } // OK +#endif Index: clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS-expected-error-on-address.c =================================================================== --- /dev/null +++ clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS-expected-error-on-address.c @@ -0,0 +1,21 @@ +// RUN: not %clang -S -emit-llvm -c -O1 -o - %s -target aarch64-gnu-linux \ +// RUN: -march=armv8-a+sve -msve-vector-bits=256 |& FileCheck %s +// REQUIRES: aarch64-registered-target + +// Examples taken from section 3.7.3.3 of the SVE ACLE (Version +// 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest + +#include <arm_sve.h> + +// Page 29, item 1. The compiler should emit a error when using +// expression like &x[0] or &x[1]. +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_PREDICATE_OPERATORS +typedef svbool_t pred __attribute__((arm_sve_vector_bits(256))); +pred x; +void h(char *); +void j() { + // CHECK: error: address of vector element requested + h((char)&x[0]); +} +#endif Index: clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_PREDICATE_OPERATORS.cpp =================================================================== --- /dev/null +++ clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_PREDICATE_OPERATORS.cpp @@ -0,0 +1,18 @@ +// RUN: %clang -x c++ -S -emit-llvm -c -O1 -o - %s -target aarch64-gnu-linux \ +// RUN: -march=armv8-a+sve -msve-vector-bits=256 | FileCheck %s +// REQUIRES: aarch64-registered-target + +// Examples taken from section 3.7.3.4 of the SVE ACLE (Version +// 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest + +#include <arm_sve.h> + +// Page 29, first paragraphs. +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_PREDICATE_OPERATORS +// CHECK-LABEL: define {{.*}} <vscale x 16 x i1> +// @_Z2f49__SVE_VLSIu10__SVBool_tLj256EES_(<vscale x 16 x i1> %x.coerce, <vscale +// x 16 x i1> %y.coerce) +typedef svbool_t pred __attribute__((arm_sve_vector_bits(256))); +auto f4(pred x, pred y) { return x & y; } // Returns a pred +#endif Index: clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_PREDICATE_OPERATORS.c =================================================================== --- /dev/null +++ clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_PREDICATE_OPERATORS.c @@ -0,0 +1,37 @@ +// RUN: %clang -S -emit-llvm -c -O1 -o - %s -target aarch64-gnu-linux \ +// RUN: -march=armv8-a+sve -msve-vector-bits=256 | FileCheck %s +// REQUIRES: aarch64-registered-target + +// Examples taken from section 3.7.3.4 of the SVE ACLE (Version +// 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest + +#include <arm_sve.h> + +// Page 29, item 2. +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_PREDICATE_OPERATORS +typedef svbool_t predty __attribute__((arm_sve_vector_bits(256))); +// CHECK-LABEL: @a = dso_local local_unnamed_addr global <4 x i8> <i8 0, i8 1, i8 0, i8 0> +predty a = {0, 1}; +#endif + +// Page 29, item 1. +// +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_PREDICATE_OPERATORS +typedef svbool_t pred __attribute__((arm_sve_vector_bits(256))); +pred x; +// CHECK-LABEL: @x = dso_local local_unnamed_addr global <4 x i8> +// zeroinitializer +// CHECK-LABEL: define dso_local i1 @f5() +// CHECK-NEXT: entry: +// CHECK-NEXT: %0 = load <4 x i8>, <4 x i8>* @x +// CHECK-NEXT: insertelement <4 x i8> %0, i8 1, i32 1 +// CHECK-NEXT: store <4 x i8> %vecins, <4 x i8>* @x +// CHECK-NEXT: extractelement <4 x i8> %0, i32 0 +// CHECK-NEXT: %tobool = icmp ne i8 %vecext, 0 +// CHECK-NEXT: ret i1 %tobool +bool f5() { + x[1] = true; + return x[0]; +} +#endif Index: clang/lib/Basic/Targets/AArch64.cpp =================================================================== --- clang/lib/Basic/Targets/AArch64.cpp +++ clang/lib/Basic/Targets/AArch64.cpp @@ -377,8 +377,11 @@ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - if (Opts.ArmSveVectorBits) + if (Opts.ArmSveVectorBits) { Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.ArmSveVectorBits)); + Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS"); + Builder.defineMacro("__ARM_FEATURE_SVE_PREDICATE_OPERATORS"); + } } ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
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