steven.zhang added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10054
+
+ case Intrinsic::ppc_altivec_mtvsrbm: {
+ // The llvm.ppc.altivec.mtvsrbm intrinsic can correspond to two different
----------------
Can we handle this inside the .td ? i.e. change the definition of the instr as:
```
def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u8imm64:$D),
"mtvsrbmi $vD, $D", IIC_VecGeneral,
[(set v16i8:$vD,
(int_ppc_altivec_mtvsrbm imm:$D))]>;
```
And add the missing u8imm64 as what we did for u16imm64 ?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82725/new/
https://reviews.llvm.org/D82725
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