fpallares added inline comments.
================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386
+ CheckReg = Inst.getOperand(3).getReg();
}
+ if (DestReg == CheckReg)
----------------
fpallares wrote:
> With the suggestion above, this could be further simplified to:
>
> ```
> if ((TargetFlags & RISCV::OneInput && Inst.getNumOperands() == 3) ||
> Inst.getNumOperands() == 4)
> return Error(Loc, "The destination vector register group cannot
> overlap"
> " the mask register.");
> ```
I see you have updated the patch and removed the `if` that checked whether we
were dealing with the masked versions of the instructions (by checking the
number of operands). IIUC that check is still necessary so we don't report an
error for unmasked instruction.
For example, from my understanding the following instruction is correct, but we
will be reporting an error.
```
viota.m v0, v2
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80802/new/
https://reviews.llvm.org/D80802
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