efriedma added a subscriber: tgt.
efriedma added a comment.
> that's fine but I still don't understand why the counterexample to my version
> says %x2 in @src can be undef
If I'm understanding correctly, this reduces to something like the following:
define i32 @src() {
%x2 = freeze i32 undef
ret i32 %x2
}
define i32 @tgt() {
ret i32 undef
}
This seems a little suspect, yes.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83360/new/
https://reviews.llvm.org/D83360
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