yroux added inline comments.
================
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5606
+ // candidates.
+ auto CantGuaranteeValueAcrossCall = [&TRI](outliner::Candidate &C) {
+ // If the unsafe registers in this block are all dead, then we don't need
----------------
samparker wrote:
> yroux wrote:
> > yroux wrote:
> > > samparker wrote:
> > > > Does this code work with the DSP instructions that read/write the Q and
> > > > GE flags? I have a nasty feeling that we don't model their register
> > > > usage.
> > > Good question, I'll test that
> > From what I saw in my testing of DSP instructions, these flags are handled
> > by CPSR usage, so this code seems good to me, do you have something else in
> > mind ?
> Ah, good, then could you please add a couple of tests for those instructions?
> I think my last concern is back with low-overhead loops and tail-predication.
> I think we should explicitly avoid outlining any MVE instructions and, if
> this pass can, then also don't move pseudo instructions too.
OK, do you know a pretty way to check if an instruction is a MVE one or a
pseudo ? If not I'll add a new helper isMVEOpcode...
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D76066/new/
https://reviews.llvm.org/D76066
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