This revision was automatically updated to reflect the committed changes.
Closed by commit rGa4dac6d4e0ea: [SveEmitter] Add builtins for svmov_b and
svnot_b. (authored by sdesmalen).
Herald added a project: clang.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D79039/new/
https://reviews.llvm.org/D79039
Files:
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
===================================================================
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
@@ -219,3 +219,11 @@
// CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svnot,_u64,_x,)(pg, op);
}
+
+svbool_t test_svnot_b_z(svbool_t pg, svbool_t op)
+{
+ // CHECK-LABEL: test_svnot_b_z
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1>
@llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op,
<vscale x 16 x i1> %pg)
+ // CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
+ return SVE_ACLE_FUNC(svnot,_b,_z,)(pg, op);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svmov_b_z(svbool_t pg, svbool_t op)
+{
+ // CHECK-LABEL: test_svmov_b_z
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1>
@llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op,
<vscale x 16 x i1> %op)
+ // CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
+ return SVE_ACLE_FUNC(svmov,_b,_z,)(pg, op);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -7990,6 +7990,23 @@
switch (BuiltinID) {
default:
return nullptr;
+
+ case SVE::BI__builtin_sve_svmov_b_z: {
+ // svmov_b_z(pg, op) <=> svand_b_z(pg, op, op)
+ SVETypeFlags TypeFlags(Builtin->TypeModifier);
+ llvm::Type* OverloadedTy = getSVEType(TypeFlags);
+ Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_and_z, OverloadedTy);
+ return Builder.CreateCall(F, {Ops[0], Ops[1], Ops[1]});
+ }
+
+ case SVE::BI__builtin_sve_svnot_b_z: {
+ // svnot_b_z(pg, op) <=> sveor_b_z(pg, op, pg)
+ SVETypeFlags TypeFlags(Builtin->TypeModifier);
+ llvm::Type* OverloadedTy = getSVEType(TypeFlags);
+ Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_eor_z, OverloadedTy);
+ return Builder.CreateCall(F, {Ops[0], Ops[1], Ops[0]});
+ }
+
case SVE::BI__builtin_sve_svpfalse_b:
return ConstantInt::getFalse(Ty);
Index: clang/include/clang/Basic/arm_sve.td
===================================================================
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -984,8 +984,10 @@
def SVAND_B_Z : SInst<"svand[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_and_z">;
def SVBIC_B_Z : SInst<"svbic[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_bic_z">;
def SVEOR_B_Z : SInst<"sveor[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_eor_z">;
+def SVMOV_B_Z : SInst<"svmov[_b]_z", "PPP", "Pc", MergeNone>; // Uses
custom expansion
def SVNAND_B_Z : SInst<"svnand[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_nand_z">;
def SVNOR_B_Z : SInst<"svnor[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_nor_z">;
+def SVNOT_B_Z : SInst<"svnot[_b]_z", "PPP", "Pc", MergeNone>; // Uses
custom expansion
def SVORN_B_Z : SInst<"svorn[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_orn_z">;
def SVORR_B_Z : SInst<"svorr[_b]_z", "PPPP", "Pc", MergeNone,
"aarch64_sve_orr_z">;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
===================================================================
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c
@@ -219,3 +219,11 @@
// CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svnot,_u64,_x,)(pg, op);
}
+
+svbool_t test_svnot_b_z(svbool_t pg, svbool_t op)
+{
+ // CHECK-LABEL: test_svnot_b_z
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op, <vscale x 16 x i1> %pg)
+ // CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
+ return SVE_ACLE_FUNC(svnot,_b,_z,)(pg, op);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svmov_b_z(svbool_t pg, svbool_t op)
+{
+ // CHECK-LABEL: test_svmov_b_z
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op, <vscale x 16 x i1> %op)
+ // CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
+ return SVE_ACLE_FUNC(svmov,_b,_z,)(pg, op);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -7990,6 +7990,23 @@
switch (BuiltinID) {
default:
return nullptr;
+
+ case SVE::BI__builtin_sve_svmov_b_z: {
+ // svmov_b_z(pg, op) <=> svand_b_z(pg, op, op)
+ SVETypeFlags TypeFlags(Builtin->TypeModifier);
+ llvm::Type* OverloadedTy = getSVEType(TypeFlags);
+ Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_and_z, OverloadedTy);
+ return Builder.CreateCall(F, {Ops[0], Ops[1], Ops[1]});
+ }
+
+ case SVE::BI__builtin_sve_svnot_b_z: {
+ // svnot_b_z(pg, op) <=> sveor_b_z(pg, op, pg)
+ SVETypeFlags TypeFlags(Builtin->TypeModifier);
+ llvm::Type* OverloadedTy = getSVEType(TypeFlags);
+ Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_eor_z, OverloadedTy);
+ return Builder.CreateCall(F, {Ops[0], Ops[1], Ops[0]});
+ }
+
case SVE::BI__builtin_sve_svpfalse_b:
return ConstantInt::getFalse(Ty);
Index: clang/include/clang/Basic/arm_sve.td
===================================================================
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -984,8 +984,10 @@
def SVAND_B_Z : SInst<"svand[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_and_z">;
def SVBIC_B_Z : SInst<"svbic[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_bic_z">;
def SVEOR_B_Z : SInst<"sveor[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_eor_z">;
+def SVMOV_B_Z : SInst<"svmov[_b]_z", "PPP", "Pc", MergeNone>; // Uses custom expansion
def SVNAND_B_Z : SInst<"svnand[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_nand_z">;
def SVNOR_B_Z : SInst<"svnor[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_nor_z">;
+def SVNOT_B_Z : SInst<"svnot[_b]_z", "PPP", "Pc", MergeNone>; // Uses custom expansion
def SVORN_B_Z : SInst<"svorn[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_orn_z">;
def SVORR_B_Z : SInst<"svorr[_b]_z", "PPPP", "Pc", MergeNone, "aarch64_sve_orr_z">;
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