fanjinke marked an inline comment as done.
fanjinke added inline comments.
================
Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85
+ (Ecx == signature_HYGON_ecx);
+ if (!IsIntel && !IsAMD && !IsHygon)
return false;
----------------
craig.topper wrote:
> fanjinke wrote:
> > craig.topper wrote:
> > > What's the rationale for the vendor check here anyway? Why isn't the bit
> > > in ecx sufficient?
> > Using the cpuid instruction to get the vendor id will return the ASCII code
> > of the vendor id, which is stored in the ebx,ecx,edx registers.
> > The ASCII code in the Hygon CPU is "HygonGenuine", the ecx = "eniu".
> > For better differentiation from other cpus in the future, by following
> > AMD/Intel way, we use full ASCII code to identify Hygon CPU.
> >
> Sorry, my question was about why this was restricted to Intel/AMD in the
> first place. Why should this code need to be updated every time a new vendor
> comes along? Why isn’t checking for sse4.2 regardless of vendor sufficient.
For this question, original author[1] may be more appropriate to reply.
From CPU specification, Bit20 of CPUID Fn0000_0001_ecx is SSE42 on Intel, AMD,
and Hygon CPUs, but we are not sure that this is true for all x86 vendors.
Cryptoad, Any comments?
[1]: https://reviews.llvm.org/D40322
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D62368/new/
https://reviews.llvm.org/D62368
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